{"total":17,"rows":[{"id":"2507.16200","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","created":"2025-07-22","cited_by_count":14,"area":null},{"id":"2504.15659","title":"VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation","created":"2025-04-22","cited_by_count":13,"area":null},{"id":"2507.13369","title":"VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation","created":"2025-07-09","cited_by_count":8,"area":null},{"id":"2512.00020","title":"Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead","created":"2025-10-29","cited_by_count":8,"area":null},{"id":"2601.21448","title":"ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design","created":"2026-01-29","cited_by_count":8,"area":null},{"id":"2601.18067","title":"EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization","created":"2026-01-26","cited_by_count":7,"area":null},{"id":"2505.19734","title":"ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection","created":"2025-05-26","cited_by_count":6,"area":null},{"id":"2510.19296","title":"QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation","created":"2025-10-22","cited_by_count":4,"area":null},{"id":"2510.21407","title":"REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models","created":"2025-10-24","cited_by_count":4,"area":null},{"id":"2505.06096","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","created":"2025-05-09","cited_by_count":2,"area":null},{"id":"2508.13156","title":"EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code","created":"2025-06-26","cited_by_count":2,"area":null},{"id":"2606.05253","title":"Alpha-RTL: Test-Time Training for RTL Hardware Optimization","created":"2026-06-03","cited_by_count":2,"area":null},{"id":"2604.17102","title":"Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation","created":"2026-04-18","cited_by_count":1,"area":null},{"id":"2604.18445","title":"AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning","created":"2026-04-20","cited_by_count":0,"area":null},{"id":"2604.23355","title":"LEGO: An LLM Skill-Based Front-End Design Generation Platform","created":"2026-04-25","cited_by_count":0,"area":null},{"id":"2606.13706","title":"HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification","created":"2026-06-09","cited_by_count":0,"area":null},{"id":"2607.29283","title":"RTLCurator: Label-Efficient Data Curation for RTL Generation","created":"2026-07-31","cited_by_count":0,"area":null}],"next_cursor":null}