{"total":28,"rows":[{"id":"2411.04732","title":"Convolutional Differentiable Logic Gate Networks","created":"2024-11-07","cited_by_count":37,"area":null},{"id":"2504.00592","title":"NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference","created":"2025-04-01","cited_by_count":14,"area":null},{"id":"2510.03250","title":"Light Differentiable Logic Gate Networks","created":"2025-09-26","cited_by_count":9,"area":null},{"id":"2510.15655","title":"WARP-LUTs -- Walsh-Assisted Relaxation for Probabilistic Look Up Tables","created":"2025-10-17","cited_by_count":6,"area":null},{"id":"2511.12340","title":"LILogic Net: Compact Logic Gate Networks with Learnable Connectivity for Efficient Hardware Deployment","created":"2025-11-15","cited_by_count":6,"area":null},{"id":"2507.02585","title":"Scalable Interconnect Learning in Boolean Networks","created":"2025-07-03","cited_by_count":4,"area":null},{"id":"2511.00812","title":"LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neurons","created":"2025-11-02","cited_by_count":3,"area":null},{"id":"2602.03527","title":"WARP Logic Neural Networks","created":"2026-02-03","cited_by_count":2,"area":null},{"id":"2508.21394","title":"AI Compute Architecture and Evolution Trends","created":"2025-08-29","cited_by_count":1,"area":null},{"id":"2512.01467","title":"Differentiable Weightless Controllers: Learning Logic Circuits for Continuous Control","created":"2025-12-01","cited_by_count":1,"area":null},{"id":"2601.11433","title":"Inter-patient ECG Arrhythmia Classification with LGNs and LUTNs","created":"2026-01-16","cited_by_count":1,"area":null},{"id":"2601.19940","title":"Continuous-Flow Data-Rate-Aware CNN Inference on FPGA","created":"2026-01-16","cited_by_count":1,"area":null},{"id":"2602.05830","title":"Learning Compact Boolean Networks","created":"2026-02-05","cited_by_count":1,"area":null},{"id":"2602.07400","title":"BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networks","created":"2026-02-07","cited_by_count":1,"area":null},{"id":"2604.22293","title":"HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference","created":"2026-04-24","cited_by_count":1,"area":null},{"id":"2607.08427","title":"FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs","created":"2026-07-09","cited_by_count":1,"area":null},{"id":"2411.01818","title":"Shrinking the Giant : Quasi-Weightless Transformers for Low Energy Inference","created":"2024-11-04","cited_by_count":0,"area":null},{"id":"2511.05479","title":"Quantization Effects of Artificial Neural Networks for Embedded Edge-Computing Applications","created":"2025-11-07","cited_by_count":0,"area":null},{"id":"2512.04189","title":"BEP: A Binary Error Propagation Algorithm for Binary Neural Networks Training","created":"2025-12-03","cited_by_count":0,"area":null},{"id":"2601.09773","title":"Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization","created":"2026-01-14","cited_by_count":0,"area":null},{"id":"2603.07606","title":"TT-Sparse: Learning Sparse Rule Models with Differentiable Truth Tables","created":"2026-03-08","cited_by_count":0,"area":null},{"id":"2603.15717","title":"GLANCE: Gaze-Led Attention Network for Compressed Edge-inference","created":"2026-03-16","cited_by_count":0,"area":null},{"id":"2603.22770","title":"From Arithmetic to Logic: The Resilience of Logic and Lookup-Based Neural Networks Under Parameter Bit-Flips","created":"2026-03-24","cited_by_count":0,"area":null},{"id":"2605.08657","title":"Fitting Multilinear Polynomials for Logic Gate Networks","created":"2026-05-09","cited_by_count":0,"area":null},{"id":"2608.00720","title":"CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs","created":"2026-08-01","cited_by_count":0,"area":null},{"id":"2609.09254","title":"DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity","created":"2026-09-08","cited_by_count":0,"area":null},{"id":"2609.33747","title":"Task-Aware Discretization of Differentiable Logic Gate Networks","created":"2026-09-27","cited_by_count":0,"area":null},{"id":"2610.01069","title":"Overcoming Kernel Redundancy for Scaling Logic Gate Networks","created":"2026-10-01","cited_by_count":0,"area":null}],"next_cursor":null}