{"total":16,"rows":[{"id":"2405.14918","title":"AnalogCoder: Analog Circuit Design via Training-Free Code Generation","created":"2024-05-23","cited_by_count":84,"area":null},{"id":"2409.11414","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","created":"2024-09-04","cited_by_count":31,"area":null},{"id":"2405.07061","title":"LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust","created":"2024-05-11","cited_by_count":20,"area":null},{"id":"2508.02518","title":"AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs","created":"2025-08-04","cited_by_count":15,"area":null},{"id":"2507.16200","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","created":"2025-07-22","cited_by_count":14,"area":null},{"id":"2407.08473","title":"Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation","created":"2024-07-11","cited_by_count":11,"area":null},{"id":"2504.19959","title":"From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification","created":"2025-04-28","cited_by_count":9,"area":null},{"id":"2508.05266","title":"Understanding and Mitigating Errors of LLM-Generated RTL Code","created":"2025-08-07","cited_by_count":8,"area":null},{"id":"2505.19734","title":"ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection","created":"2025-05-26","cited_by_count":6,"area":null},{"id":"2507.21485","title":"HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions","created":"2025-07-29","cited_by_count":5,"area":null},{"id":"2411.13802","title":"SemiKong: Curating, Training, and Evaluating A Semiconductor Industry-Specific Large Language Model","created":"2024-11-21","cited_by_count":4,"area":null},{"id":"2407.18326","title":"Classification-Based Automatic HDL Code Generation Using LLMs","created":"2024-07-04","cited_by_count":3,"area":null},{"id":"2604.27643","title":"HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs","created":"2026-04-30","cited_by_count":2,"area":null},{"id":"2407.12576","title":"IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA","created":"2024-07-17","cited_by_count":1,"area":null},{"id":"2606.23759","title":"VeriPilot: An LLM-Powered Verilog Debugging Framework","created":"2026-06-22","cited_by_count":1,"area":null},{"id":"2610.03971","title":"An Executable Benchmark for LLM-Based HLS Repair:Design Complexity and Repair Underconstraint","created":"2026-10-02","cited_by_count":0,"area":null}],"next_cursor":null}