{"total":100,"rows":[{"id":"2408.08927","title":"VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool","created":"2024-08-15","cited_by_count":85,"area":"agents"},{"id":"2405.14918","title":"AnalogCoder: Analog Circuit Design via Training-Free Code Generation","created":"2024-05-23","cited_by_count":84,"area":null},{"id":"2407.16237","title":"OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection","created":"2024-07-23","cited_by_count":56,"area":null},{"id":"2409.12993","title":"CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair","created":"2024-09-19","cited_by_count":42,"area":"synth"},{"id":"2501.09655","title":"A Survey of Research in Large Language Models for Electronic Design Automation","created":"2025-01-16","cited_by_count":41,"area":null},{"id":"2407.10424","title":"CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization","created":"2024-07-15","cited_by_count":38,"area":null},{"id":"2407.18333","title":"AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs","created":"2024-07-21","cited_by_count":36,"area":null},{"id":"2409.11414","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","created":"2024-09-04","cited_by_count":31,"area":null},{"id":"2412.07822","title":"MAGE: A Multi-Agent Engine for Automated RTL Code Generation","created":"2024-12-10","cited_by_count":31,"area":"agents"},{"id":"2407.15353","title":"Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA","created":"2024-07-22","cited_by_count":28,"area":"rag"},{"id":"2403.11671","title":"HDLdebugger: Streamlining HDL debugging with Large Language Models","created":"2024-03-18","cited_by_count":26,"area":null},{"id":"2502.15832","title":"DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model","created":"2025-02-20","cited_by_count":23,"area":null},{"id":"2506.05566","title":"ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation","created":"2025-06-05","cited_by_count":22,"area":"lr"},{"id":"2405.07061","title":"LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust","created":"2024-05-11","cited_by_count":20,"area":null},{"id":"2411.11856","title":"Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback","created":"2024-11-01","cited_by_count":19,"area":null},{"id":"2412.06947","title":"PyraNet: A Multi-Layered Hierarchical Dataset for Verilog","created":"2024-12-09","cited_by_count":19,"area":null},{"id":"2505.13479","title":"RTL++: Graph-enhanced LLM for RTL Code Generation","created":"2025-05-11","cited_by_count":18,"area":null},{"id":"2503.16528","title":"HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL","created":"2025-03-18","cited_by_count":17,"area":"rag"},{"id":"2505.11849","title":"VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation","created":"2025-05-17","cited_by_count":16,"area":"lr"},{"id":"2407.18271","title":"Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning","created":"2024-07-21","cited_by_count":15,"area":null},{"id":"2508.02518","title":"AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs","created":"2025-08-04","cited_by_count":15,"area":null},{"id":"2504.15804","title":"Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback","created":"2025-04-22","cited_by_count":14,"area":"alignment"},{"id":"2507.16200","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","created":"2025-07-22","cited_by_count":14,"area":null},{"id":"2504.15659","title":"VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation","created":"2025-04-22","cited_by_count":13,"area":null},{"id":"2503.13572","title":"VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination","created":"2025-03-17","cited_by_count":12,"area":null},{"id":"2503.16514","title":"VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric","created":"2025-03-15","cited_by_count":12,"area":"agents"},{"id":"2504.14560","title":"ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model","created":"2025-04-20","cited_by_count":12,"area":"lr"},{"id":"2508.20134","title":"QAgent: An LLM-based Multi-Agent System for Autonomous OpenQASM programming","created":"2025-08-26","cited_by_count":11,"area":"agents"},{"id":"2409.15186","title":"Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog","created":"2024-09-23","cited_by_count":10,"area":null},{"id":"2506.15697","title":"DeepRTL2: A Versatile Model for RTL-Related Tasks","created":"2025-05-28","cited_by_count":10,"area":null},{"id":"2407.12022","title":"ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generation","created":"2024-06-28","cited_by_count":9,"area":null},{"id":"2412.11014","title":"CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation","created":"2024-12-15","cited_by_count":9,"area":"agents"},{"id":"2504.01986","title":"TuRTLe: A Unified Evaluation of LLMs for RTL Generation","created":"2025-03-31","cited_by_count":9,"area":null},{"id":"2504.09260","title":"NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph","created":"2025-04-12","cited_by_count":9,"area":null},{"id":"2509.04905","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","created":"2025-09-05","cited_by_count":9,"area":null},{"id":"2502.12732","title":"Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment","created":"2025-02-18","cited_by_count":8,"area":null},{"id":"2507.13369","title":"VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation","created":"2025-07-09","cited_by_count":8,"area":null},{"id":"2508.05266","title":"Understanding and Mitigating Errors of LLM-Generated RTL Code","created":"2025-08-07","cited_by_count":8,"area":null},{"id":"2512.00020","title":"Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead","created":"2025-10-29","cited_by_count":8,"area":null},{"id":"2504.08862","title":"RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentation","created":"2025-04-11","cited_by_count":7,"area":"rag"},{"id":"2505.22086","title":"iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs","created":"2025-05-28","cited_by_count":7,"area":null},{"id":"2604.14989","title":"Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement","created":"2026-04-16","cited_by_count":6,"area":"agents"},{"id":"2403.13838","title":"Circuit Transformer: A Transformer That Preserves Logical Equivalence","created":"2024-03-14","cited_by_count":5,"area":null},{"id":"2507.02226","title":"DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs","created":"2025-07-03","cited_by_count":5,"area":null},{"id":"2507.04736","title":"ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning","created":"2025-07-07","cited_by_count":5,"area":"lr"},{"id":"2510.15899","title":"LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models","created":"2025-09-10","cited_by_count":5,"area":null},{"id":"2510.19296","title":"QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation","created":"2025-10-22","cited_by_count":4,"area":null},{"id":"2510.21407","title":"REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models","created":"2025-10-24","cited_by_count":4,"area":null},{"id":"2512.05371","title":"ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications","created":"2025-12-05","cited_by_count":4,"area":"lr"},{"id":"2601.07593","title":"GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation","created":"2026-01-12","cited_by_count":4,"area":"lr"},{"id":"2603.17613","title":"VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generation","created":"2026-03-18","cited_by_count":4,"area":"agents"},{"id":"2407.18326","title":"Classification-Based Automatic HDL Code Generation Using LLMs","created":"2024-07-04","cited_by_count":3,"area":null},{"id":"2411.00843","title":"The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation","created":"2024-10-30","cited_by_count":3,"area":null},{"id":"2506.07239","title":"VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code","created":"2025-06-08","cited_by_count":3,"area":null},{"id":"2601.19747","title":"Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation","created":"2026-01-27","cited_by_count":3,"area":"agents"},{"id":"2602.04195","title":"Semantic Consensus Decoding: Backdoor Defense for Verilog Code Generation","created":"2026-02-04","cited_by_count":3,"area":"safety"},{"id":"2604.15001","title":"COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation","created":"2026-04-16","cited_by_count":3,"area":null},{"id":"2505.06096","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","created":"2025-05-09","cited_by_count":2,"area":null},{"id":"2506.04544","title":"hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation","created":"2025-06-05","cited_by_count":2,"area":null},{"id":"2508.12910","title":"SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip","created":"2025-08-18","cited_by_count":2,"area":null},{"id":"2508.13156","title":"EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code","created":"2025-06-26","cited_by_count":2,"area":null},{"id":"2510.15914","title":"VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts","created":"2025-09-27","cited_by_count":2,"area":null},{"id":"2511.12033","title":"EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation","created":"2025-11-15","cited_by_count":2,"area":null},{"id":"2605.15537","title":"RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision","created":"2026-05-15","cited_by_count":2,"area":"agents"},{"id":"2606.05253","title":"Alpha-RTL: Test-Time Training for RTL Hardware Optimization","created":"2026-06-03","cited_by_count":2,"area":null},{"id":"2410.16119","title":"SeaDAG: Semi-autoregressive Diffusion for Conditional Directed Acyclic Graph Generation","created":"2024-10-21","cited_by_count":1,"area":"diffusion"},{"id":"2504.05180","title":"BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks","created":"2025-04-07","cited_by_count":1,"area":null},{"id":"2504.09485","title":"GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment","created":"2025-04-13","cited_by_count":1,"area":"lr"},{"id":"2504.14625","title":"Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence","created":"2025-04-20","cited_by_count":1,"area":"agents"},{"id":"2506.07945","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","created":"2025-06-09","cited_by_count":1,"area":null},{"id":"2508.05675","title":"Principle-Guided Verilog Optimization: IP-Safe Knowledge Transfer via Local-Cloud Collaboration","created":"2025-08-05","cited_by_count":1,"area":null},{"id":"2508.18730","title":"Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning","created":"2025-08-26","cited_by_count":1,"area":null},{"id":"2510.05327","title":"DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base","created":"2025-10-06","cited_by_count":1,"area":"rag"},{"id":"2510.08664","title":"Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware","created":"2025-10-09","cited_by_count":1,"area":null},{"id":"2511.20099","title":"QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design","created":"2025-11-25","cited_by_count":1,"area":null},{"id":"2512.05073","title":"David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?","created":"2025-12-04","cited_by_count":1,"area":"agents"},{"id":"2512.11398","title":"AutoFSM: A Multi-agent Framework for FSM Code Generation with IR and SystemC-Based Testing","created":"2025-12-12","cited_by_count":1,"area":"agents"},{"id":"2602.00704","title":"QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generation","created":"2026-01-31","cited_by_count":1,"area":null},{"id":"2604.23602","title":"TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog","created":"2026-04-26","cited_by_count":1,"area":null},{"id":"2605.12857","title":"ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation","created":"2026-05-13","cited_by_count":1,"area":"agents"},{"id":"2606.08976","title":"RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models","created":"2026-06-08","cited_by_count":1,"area":"lr"},{"id":"2608.30659","title":"LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflow","created":"2026-08-31","cited_by_count":1,"area":"agents"},{"id":"2503.11662","title":"Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language","created":"2025-02-14","cited_by_count":0,"area":null},{"id":"2503.21971","title":"RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts","created":"2025-03-27","cited_by_count":0,"area":"moe"},{"id":"2504.19144","title":"ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development","created":"2025-04-27","cited_by_count":0,"area":"lr"},{"id":"2506.05007","title":"QiMeng: Fully Automated Hardware and Software Design for Processor Chip","created":"2025-06-05","cited_by_count":0,"area":null},{"id":"2508.18462","title":"VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning","created":"2025-08-25","cited_by_count":0,"area":null},{"id":"2509.00071","title":"SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits","created":"2025-08-26","cited_by_count":0,"area":null},{"id":"2512.00016","title":"Architect in the Loop Agentic Hardware Design and Verification","created":"2025-10-19","cited_by_count":0,"area":null},{"id":"2603.00434","title":"RTLocating: Intent-aware RTL Localization for Hardware Design Iteration","created":"2026-02-28","cited_by_count":0,"area":null},{"id":"2604.18445","title":"AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning","created":"2026-04-20","cited_by_count":0,"area":null},{"id":"2605.26498","title":"Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation","created":"2026-05-26","cited_by_count":0,"area":null},{"id":"2605.31040","title":"UniRTL: Unifying Code and Graph for Robust RTL Representation Learning","created":"2026-05-29","cited_by_count":0,"area":null},{"id":"2606.07925","title":"ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards","created":"2026-06-06","cited_by_count":0,"area":null},{"id":"2606.09867","title":"EstRTL: Functional Estimation Guided RTL Code Generation","created":"2026-06-01","cited_by_count":0,"area":null},{"id":"2606.10285","title":"OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design","created":"2026-06-09","cited_by_count":0,"area":null},{"id":"2606.15500","title":"LLM4RTL: Tool-Assisted LLM for RTL Generation","created":"2026-06-13","cited_by_count":0,"area":null},{"id":"2607.17063","title":"When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering","created":"2026-07-19","cited_by_count":0,"area":null},{"id":"2608.02878","title":"VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space","created":"2026-08-03","cited_by_count":0,"area":"agents"},{"id":"2608.02915","title":"LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension","created":"2026-08-03","cited_by_count":0,"area":"agents"}],"next_cursor":null}