{"total":22,"rows":[{"id":"2403.11671","title":"HDLdebugger: Streamlining HDL debugging with Large Language Models","created":"2024-03-18","cited_by_count":26,"area":null},{"id":"2507.16200","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","created":"2025-07-22","cited_by_count":14,"area":null},{"id":"2503.19174","title":"AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL","created":"2025-03-24","cited_by_count":13,"area":null},{"id":"2503.13572","title":"VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination","created":"2025-03-17","cited_by_count":12,"area":null},{"id":"2407.08473","title":"Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation","created":"2024-07-11","cited_by_count":11,"area":null},{"id":"2503.13116","title":"VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding","created":"2025-03-17","cited_by_count":11,"area":null},{"id":"2410.20553","title":"SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidance","created":"2024-10-27","cited_by_count":10,"area":null},{"id":"2410.23299","title":"FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware","created":"2024-10-15","cited_by_count":10,"area":null},{"id":"2503.08923","title":"Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset","created":"2025-03-11","cited_by_count":10,"area":null},{"id":"2504.09260","title":"NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph","created":"2025-04-12","cited_by_count":9,"area":null},{"id":"2504.19959","title":"From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification","created":"2025-04-28","cited_by_count":9,"area":null},{"id":"2502.12732","title":"Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment","created":"2025-02-18","cited_by_count":8,"area":null},{"id":"2502.20633","title":"Are LLMs Ready for Practical Adoption for Assertion Generation?","created":"2025-02-28","cited_by_count":6,"area":null},{"id":"2511.16395","title":"CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference","created":"2025-11-20","cited_by_count":3,"area":null},{"id":"2605.27472","title":"AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications","created":"2026-05-26","cited_by_count":3,"area":null},{"id":"2503.05951","title":"TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator","created":"2025-03-07","cited_by_count":2,"area":null},{"id":"2506.07945","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","created":"2025-06-09","cited_by_count":1,"area":null},{"id":"2506.00002","title":"Advancing AI-assisted Hardware Design with Hierarchical Decentralized Training and Personalized Inference-Time Optimization","created":"2025-04-21","cited_by_count":0,"area":null},{"id":"2605.00058","title":"Autoformalizing Memory Specifications with Agents","created":"2026-04-30","cited_by_count":0,"area":null},{"id":"2606.13706","title":"HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification","created":"2026-06-09","cited_by_count":0,"area":null},{"id":"2608.26113","title":"PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devices","created":"2026-05-28","cited_by_count":0,"area":null},{"id":"2609.33699","title":"SpecRead: A Benchmark for Measuring Whether Language Models Understand Hardware Specifications","created":"2026-09-27","cited_by_count":0,"area":null}],"next_cursor":null}