{"total":39,"rows":[{"id":"2410.20011","title":"A Survey of Small Language Models","created":"2024-10-25","cited_by_count":31,"area":null},{"id":"2406.07081","title":"Efficiently Exploring Large Language Models for Document-Level Machine Translation with In-context Learning","created":"2024-06-11","cited_by_count":23,"area":null},{"id":"2502.03304","title":"Harmony in Divergence: Towards Fast, Accurate, and Memory-efficient Zeroth-order LLM Fine-tuning","created":"2025-02-05","cited_by_count":18,"area":null},{"id":"2410.04960","title":"On Efficient Variants of Segment Anything Model: A Survey","created":"2024-10-07","cited_by_count":16,"area":null},{"id":"2406.08413","title":"Memory Is All You Need: An Overview of Compute-in-Memory Architectures for Accelerating Large Language Model Inference","created":"2024-06-12","cited_by_count":15,"area":null},{"id":"2504.20314","title":"Perturbation-efficient Zeroth-order Optimization for Hardware-friendly On-device Training","created":"2025-04-28","cited_by_count":9,"area":null},{"id":"2509.16989","title":"PTQTP: Post-Training Quantization to Trit-Planes for Large Language Models","created":"2025-09-21","cited_by_count":9,"area":null},{"id":"2603.16952","title":"Embodied Foundation Models at the Edge: A Survey of Deployment Constraints and Mitigation Strategies","created":"2026-03-16","cited_by_count":9,"area":null},{"id":"2406.10903","title":"New Solutions on LLM Acceleration, Optimization, and Application","created":"2024-06-16","cited_by_count":7,"area":null},{"id":"2502.16473","title":"TerEffic: Highly Efficient Ternary LLM Inference on FPGA","created":"2025-02-23","cited_by_count":6,"area":null},{"id":"2509.13765","title":"TENET: An Efficient Sparsity-Aware LUT-Centric Architecture for Ternary LLM Inference On Edge","created":"2025-09-17","cited_by_count":6,"area":null},{"id":"2503.11663","title":"MEADOW: Memory-efficient Dataflow and Data Packing for Low Power Edge LLMs","created":"2025-02-14","cited_by_count":4,"area":null},{"id":"2411.03697","title":"TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture","created":"2024-11-06","cited_by_count":3,"area":null},{"id":"2411.18148","title":"A Runtime-Adaptive Transformer Neural Network Accelerator on FPGAs","created":"2024-11-27","cited_by_count":3,"area":null},{"id":"2502.08807","title":"InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs","created":"2025-02-12","cited_by_count":3,"area":null},{"id":"2509.00031","title":"End-to-End On-Device Quantization-Aware Training for LLMs at Inference Cost","created":"2025-08-21","cited_by_count":3,"area":null},{"id":"2601.15710","title":"FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design","created":"2026-01-22","cited_by_count":3,"area":null},{"id":"2603.21725","title":"CurvZO: Adaptive Curvature-Guided Sparse Zeroth-Order Optimization for Efficient LLM Fine-Tuning","created":"2026-03-23","cited_by_count":3,"area":null},{"id":"2410.06722","title":"Scaling Laws For Mixed Quantization","created":"2024-10-09","cited_by_count":2,"area":null},{"id":"2411.11852","title":"LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference","created":"2024-11-01","cited_by_count":2,"area":null},{"id":"2510.15926","title":"TeLLMe v2: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs","created":"2025-10-03","cited_by_count":2,"area":null},{"id":"2510.18228","title":"Towards Fast LLM Fine-tuning through Zeroth-Order Optimization with Projected Gradient-Aligned Perturbations","created":"2025-10-21","cited_by_count":2,"area":null},{"id":"2602.04163","title":"BPDQ: Bit-Plane Decomposition Quantization on a Variable Grid for Large Language Models","created":"2026-02-04","cited_by_count":2,"area":null},{"id":"2406.06211","title":"iMotion-LLM: Instruction-Conditioned Trajectory Generation","created":"2024-06-10","cited_by_count":1,"area":null},{"id":"2409.13975","title":"ProTEA: Programmable Transformer Encoder Acceleration on FPGA","created":"2024-09-21","cited_by_count":1,"area":null},{"id":"2409.14023","title":"FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs","created":"2024-09-21","cited_by_count":1,"area":null},{"id":"2504.19323","title":"NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI","created":"2025-04-27","cited_by_count":1,"area":null},{"id":"2505.03745","title":"AccLLM: Accelerating Long-Context LLM Inference Via Algorithm-Hardware Co-Design","created":"2025-04-07","cited_by_count":1,"area":null},{"id":"2505.16335","title":"FPQVAR: Floating Point Quantization for Visual Autoregressive Model with FPGA Hardware Co-design","created":"2025-05-22","cited_by_count":1,"area":null},{"id":"2605.27435","title":"When NPUs Are Not Always Faster: A Stage-Level Analysis of Mobile LLM Inference","created":"2026-05-22","cited_by_count":1,"area":null},{"id":"2404.16158","title":"The Feasibility of Implementing Large-Scale Transformers on Multi-FPGA Platforms","created":"2024-04-24","cited_by_count":0,"area":null},{"id":"2502.15773","title":"JExplore: Design Space Exploration Tool for Nvidia Jetson Boards","created":"2025-02-16","cited_by_count":0,"area":null},{"id":"2503.16731","title":"Design and Implementation of an FPGA-Based Hardware Accelerator for Transformer","created":"2025-03-20","cited_by_count":0,"area":null},{"id":"2505.23454","title":"LCB-CV-UNet: Enhanced Detector for High Dynamic Range Radar Signals","created":"2025-05-29","cited_by_count":0,"area":null},{"id":"2605.06052","title":"XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA","created":"2026-05-07","cited_by_count":0,"area":null},{"id":"2607.03652","title":"ELiTeFormer: An Efficient Transformer for FPGAs","created":"2026-07-04","cited_by_count":0,"area":null},{"id":"2608.25321","title":"LLMscope: Extracting LLM Assets from Edge AI Chips via Optical Probing","created":"2026-08-26","cited_by_count":0,"area":null},{"id":"2609.01212","title":"Recent Developments in Transformer Inference Deployment on FPGA Platforms: A Survey","created":"2026-09-01","cited_by_count":0,"area":null},{"id":"2609.09772","title":"SymbolicLight V2: Hybrid Neuromorphic Architecture and Sparse Execution for Low-Energy Language Inference","created":"2026-09-09","cited_by_count":0,"area":null}],"next_cursor":null}