{"total":65,"rows":[{"id":"2402.03375","title":"BetterV: Controlled Verilog Generation with Discriminative Guidance","created":"2024-02-03","cited_by_count":100,"area":null},{"id":"2405.14918","title":"AnalogCoder: Analog Circuit Design via Training-Free Code Generation","created":"2024-05-23","cited_by_count":84,"area":null},{"id":"2501.09655","title":"A Survey of Research in Large Language Models for Electronic Design Automation","created":"2025-01-16","cited_by_count":41,"area":null},{"id":"2401.12224","title":"LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation","created":"2023-12-28","cited_by_count":40,"area":null},{"id":"2407.10424","title":"CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization","created":"2024-07-15","cited_by_count":38,"area":null},{"id":"2407.18333","title":"AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs","created":"2024-07-21","cited_by_count":36,"area":null},{"id":"2409.11414","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","created":"2024-09-04","cited_by_count":31,"area":null},{"id":"2403.11671","title":"HDLdebugger: Streamlining HDL debugging with Large Language Models","created":"2024-03-18","cited_by_count":26,"area":null},{"id":"2405.07061","title":"LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust","created":"2024-05-11","cited_by_count":20,"area":null},{"id":"2407.05040","title":"Code Less, Align More: Efficient LLM Fine-tuning for Code Generation with Data Pruning","created":"2024-07-06","cited_by_count":20,"area":null},{"id":"2412.06947","title":"PyraNet: A Multi-Layered Hierarchical Dataset for Verilog","created":"2024-12-09","cited_by_count":19,"area":null},{"id":"2409.11411","title":"AIvril: AI-Driven RTL Generation With Verification In-The-Loop","created":"2024-09-03","cited_by_count":15,"area":null},{"id":"2508.02518","title":"AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs","created":"2025-08-04","cited_by_count":15,"area":null},{"id":"2507.16200","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","created":"2025-07-22","cited_by_count":14,"area":null},{"id":"2405.06676","title":"EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD","created":"2024-05-04","cited_by_count":13,"area":null},{"id":"2504.15659","title":"VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation","created":"2025-04-22","cited_by_count":13,"area":null},{"id":"2504.19099","title":"VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction","created":"2025-04-27","cited_by_count":12,"area":null},{"id":"2407.08473","title":"Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation","created":"2024-07-11","cited_by_count":11,"area":null},{"id":"2410.23299","title":"FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware","created":"2024-10-15","cited_by_count":10,"area":null},{"id":"2504.01986","title":"TuRTLe: A Unified Evaluation of LLMs for RTL Generation","created":"2025-03-31","cited_by_count":9,"area":null},{"id":"2504.19959","title":"From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification","created":"2025-04-28","cited_by_count":9,"area":null},{"id":"2509.04905","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","created":"2025-09-05","cited_by_count":9,"area":null},{"id":"2502.12732","title":"Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment","created":"2025-02-18","cited_by_count":8,"area":null},{"id":"2508.05266","title":"Understanding and Mitigating Errors of LLM-Generated RTL Code","created":"2025-08-07","cited_by_count":8,"area":null},{"id":"2512.00020","title":"Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead","created":"2025-10-29","cited_by_count":8,"area":null},{"id":"2406.10903","title":"New Solutions on LLM Acceleration, Optimization, and Application","created":"2024-06-16","cited_by_count":7,"area":null},{"id":"2408.16018","title":"SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection","created":"2024-08-25","cited_by_count":7,"area":null},{"id":"2505.22086","title":"iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs","created":"2025-05-28","cited_by_count":7,"area":null},{"id":"2508.13157","title":"Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlists","created":"2025-06-27","cited_by_count":7,"area":null},{"id":"2505.19734","title":"ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection","created":"2025-05-26","cited_by_count":6,"area":null},{"id":"2411.19043","title":"Using a Feedback Loop for LLM-based Infrastructure as Code Generation","created":"2024-11-28","cited_by_count":5,"area":null},{"id":"2507.21485","title":"HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions","created":"2025-07-29","cited_by_count":5,"area":null},{"id":"2407.05036","title":"Enhance the Robustness of Text-Centric Multimodal Alignments","created":"2024-07-06","cited_by_count":4,"area":null},{"id":"2411.13802","title":"SemiKong: Curating, Training, and Evaluating A Semiconductor Industry-Specific Large Language Model","created":"2024-11-21","cited_by_count":4,"area":null},{"id":"2505.07309","title":"Uncertainty Profiles for LLMs: Uncertainty Source Decomposition and Adaptive Model-Metric Selection","created":"2025-05-12","cited_by_count":4,"area":null},{"id":"2507.06512","title":"Towards LLM-based Root Cause Analysis of Hardware Design Failures","created":"2025-07-09","cited_by_count":4,"area":null},{"id":"2407.18326","title":"Classification-Based Automatic HDL Code Generation Using LLMs","created":"2024-07-04","cited_by_count":3,"area":null},{"id":"2411.00843","title":"The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation","created":"2024-10-30","cited_by_count":3,"area":null},{"id":"2506.07239","title":"VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code","created":"2025-06-08","cited_by_count":3,"area":null},{"id":"2508.20030","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","created":"2025-08-27","cited_by_count":3,"area":null},{"id":"2510.14756","title":"Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code","created":"2025-10-16","cited_by_count":3,"area":null},{"id":"2505.06096","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","created":"2025-05-09","cited_by_count":2,"area":null},{"id":"2507.10639","title":"Evaluating LLM-based Workflows for Switched-Mode Power Supply Design","created":"2025-07-14","cited_by_count":2,"area":null},{"id":"2508.13156","title":"EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code","created":"2025-06-26","cited_by_count":2,"area":null},{"id":"2508.19393","title":"GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification","created":"2025-08-26","cited_by_count":2,"area":null},{"id":"2511.12033","title":"EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation","created":"2025-11-15","cited_by_count":2,"area":null},{"id":"2604.27643","title":"HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs","created":"2026-04-30","cited_by_count":2,"area":null},{"id":"2407.12749","title":"ChipXplore: Natural Language Exploration of Hardware Designs and Libraries","created":"2024-07-17","cited_by_count":1,"area":null},{"id":"2407.18423","title":"HDL-GPT: High-Quality HDL is All You Need","created":"2024-07-25","cited_by_count":1,"area":null},{"id":"2507.16808","title":"Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosis","created":"2025-07-22","cited_by_count":1,"area":null},{"id":"2510.15872","title":"Multimodal Chip Physical Design Engineer Assistant","created":"2025-07-02","cited_by_count":1,"area":null},{"id":"2606.23759","title":"VeriPilot: An LLM-Powered Verilog Debugging Framework","created":"2026-06-22","cited_by_count":1,"area":null},{"id":"2608.27184","title":"LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration","created":"2026-08-27","cited_by_count":1,"area":null},{"id":"2412.04485","title":"EDA-Aware RTL Generation with Large Language Models","created":"2024-11-21","cited_by_count":0,"area":null},{"id":"2503.11662","title":"Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language","created":"2025-02-14","cited_by_count":0,"area":null},{"id":"2506.00002","title":"Advancing AI-assisted Hardware Design with Hierarchical Decentralized Training and Personalized Inference-Time Optimization","created":"2025-04-21","cited_by_count":0,"area":null},{"id":"2506.05007","title":"QiMeng: Fully Automated Hardware and Software Design for Processor Chip","created":"2025-06-05","cited_by_count":0,"area":null},{"id":"2508.18462","title":"VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning","created":"2025-08-25","cited_by_count":0,"area":null},{"id":"2604.18445","title":"AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning","created":"2026-04-20","cited_by_count":0,"area":null},{"id":"2604.23355","title":"LEGO: An LLM Skill-Based Front-End Design Generation Platform","created":"2026-04-25","cited_by_count":0,"area":null},{"id":"2605.01338","title":"DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams","created":"2026-05-02","cited_by_count":0,"area":null},{"id":"2605.26498","title":"Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation","created":"2026-05-26","cited_by_count":0,"area":null},{"id":"2606.09867","title":"EstRTL: Functional Estimation Guided RTL Code Generation","created":"2026-06-01","cited_by_count":0,"area":null},{"id":"2607.17063","title":"When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering","created":"2026-07-19","cited_by_count":0,"area":null},{"id":"2610.03971","title":"An Executable Benchmark for LLM-Based HLS Repair:Design Complexity and Repair Underconstraint","created":"2026-10-02","cited_by_count":0,"area":null}],"next_cursor":null}