{"total":83,"rows":[{"id":"2405.14918","title":"AnalogCoder: Analog Circuit Design via Training-Free Code Generation","created":"2024-05-23","cited_by_count":84,"area":null},{"id":"2407.16237","title":"OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection","created":"2024-07-23","cited_by_count":56,"area":null},{"id":"2402.03289","title":"Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS","created":"2024-02-05","cited_by_count":43,"area":null},{"id":"2501.09655","title":"A Survey of Research in Large Language Models for Electronic Design Automation","created":"2025-01-16","cited_by_count":41,"area":null},{"id":"2401.12224","title":"LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation","created":"2023-12-28","cited_by_count":40,"area":null},{"id":"2405.02580","title":"PropertyGPT: LLM-driven Formal Verification of Smart Contracts through Retrieval-Augmented Property Generation","created":"2024-05-04","cited_by_count":37,"area":"rag"},{"id":"2503.00205","title":"AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies","created":"2025-02-28","cited_by_count":37,"area":null},{"id":"2407.18333","title":"AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs","created":"2024-07-21","cited_by_count":36,"area":null},{"id":"2407.15353","title":"Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA","created":"2024-07-22","cited_by_count":28,"area":"rag"},{"id":"2407.18276","title":"Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design","created":"2024-07-23","cited_by_count":24,"area":null},{"id":"2405.07061","title":"LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust","created":"2024-05-11","cited_by_count":20,"area":null},{"id":"2404.08806","title":"CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation","created":"2024-04-12","cited_by_count":19,"area":null},{"id":"2411.11856","title":"Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback","created":"2024-11-01","cited_by_count":19,"area":null},{"id":"2412.06947","title":"PyraNet: A Multi-Layered Hierarchical Dataset for Verilog","created":"2024-12-09","cited_by_count":19,"area":null},{"id":"2406.04373","title":"VerilogReader: LLM-Aided Hardware Test Generation","created":"2024-06-03","cited_by_count":17,"area":null},{"id":"2503.16528","title":"HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL","created":"2025-03-18","cited_by_count":17,"area":"rag"},{"id":"2406.04379","title":"VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation","created":"2024-06-06","cited_by_count":15,"area":null},{"id":"2411.17569","title":"RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation","created":"2024-11-26","cited_by_count":15,"area":"safety"},{"id":"2508.02518","title":"AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs","created":"2025-08-04","cited_by_count":15,"area":null},{"id":"2510.27617","title":"VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generation","created":"2025-10-31","cited_by_count":15,"area":"agents"},{"id":"2405.06676","title":"EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD","created":"2024-05-04","cited_by_count":13,"area":null},{"id":"2503.13572","title":"VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination","created":"2025-03-17","cited_by_count":12,"area":null},{"id":"2506.02089","title":"SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design","created":"2025-06-02","cited_by_count":12,"area":"safety"},{"id":"2503.13116","title":"VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding","created":"2025-03-17","cited_by_count":11,"area":null},{"id":"2410.20553","title":"SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidance","created":"2024-10-27","cited_by_count":10,"area":null},{"id":"2407.12022","title":"ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generation","created":"2024-06-28","cited_by_count":9,"area":null},{"id":"2503.12721","title":"Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective","created":"2025-03-17","cited_by_count":9,"area":"lr"},{"id":"2509.04905","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","created":"2025-09-05","cited_by_count":9,"area":null},{"id":"2507.13369","title":"VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation","created":"2025-07-09","cited_by_count":8,"area":null},{"id":"2508.05266","title":"Understanding and Mitigating Errors of LLM-Generated RTL Code","created":"2025-08-07","cited_by_count":8,"area":null},{"id":"2512.00020","title":"Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead","created":"2025-10-29","cited_by_count":8,"area":null},{"id":"2406.10903","title":"New Solutions on LLM Acceleration, Optimization, and Application","created":"2024-06-16","cited_by_count":7,"area":null},{"id":"2504.08862","title":"RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentation","created":"2025-04-11","cited_by_count":7,"area":"rag"},{"id":"2506.00005","title":"Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form","created":"2025-05-07","cited_by_count":7,"area":null},{"id":"2508.13157","title":"Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlists","created":"2025-06-27","cited_by_count":7,"area":null},{"id":"2505.19734","title":"ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection","created":"2025-05-26","cited_by_count":6,"area":null},{"id":"2506.10501","title":"BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis","created":"2025-06-12","cited_by_count":6,"area":"agents"},{"id":"2507.19525","title":"MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs","created":"2025-07-20","cited_by_count":6,"area":"mllm"},{"id":"2606.28279","title":"Agentic Hardware Design as Repository-Level Code Evolution","created":"2026-06-26","cited_by_count":6,"area":"agents"},{"id":"2511.22749","title":"VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimization","created":"2025-11-27","cited_by_count":5,"area":null},{"id":"2512.11611","title":"Using GUI Agent for Electronic Design Automation","created":"2025-12-12","cited_by_count":5,"area":"agents"},{"id":"2601.07593","title":"GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation","created":"2026-01-12","cited_by_count":4,"area":"lr"},{"id":"2407.18326","title":"Classification-Based Automatic HDL Code Generation Using LLMs","created":"2024-07-04","cited_by_count":3,"area":null},{"id":"2501.02446","title":"RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework","created":"2025-01-05","cited_by_count":3,"area":"safety"},{"id":"2511.16395","title":"CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference","created":"2025-11-20","cited_by_count":3,"area":null},{"id":"2601.19747","title":"Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation","created":"2026-01-27","cited_by_count":3,"area":"agents"},{"id":"2602.04195","title":"Semantic Consensus Decoding: Backdoor Defense for Verilog Code Generation","created":"2026-02-04","cited_by_count":3,"area":"safety"},{"id":"2503.05951","title":"TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator","created":"2025-03-07","cited_by_count":2,"area":null},{"id":"2505.06096","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","created":"2025-05-09","cited_by_count":2,"area":null},{"id":"2507.10639","title":"Evaluating LLM-based Workflows for Switched-Mode Power Supply Design","created":"2025-07-14","cited_by_count":2,"area":null},{"id":"2508.13156","title":"EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code","created":"2025-06-26","cited_by_count":2,"area":null},{"id":"2603.17204","title":"CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization","created":"2026-03-17","cited_by_count":2,"area":"agents"},{"id":"2405.02329","title":"Digital ASIC Design with Ongoing LLMs: Strategies and Prospects","created":"2024-04-25","cited_by_count":1,"area":null},{"id":"2407.12576","title":"IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA","created":"2024-07-17","cited_by_count":1,"area":null},{"id":"2504.05180","title":"BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks","created":"2025-04-07","cited_by_count":1,"area":null},{"id":"2505.09610","title":"Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors","created":"2025-05-14","cited_by_count":1,"area":null},{"id":"2506.00001","title":"Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering Techniques","created":"2025-03-26","cited_by_count":1,"area":null},{"id":"2510.05327","title":"DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base","created":"2025-10-06","cited_by_count":1,"area":"rag"},{"id":"2511.17833","title":"Learning to Debug: LLM-Organized Knowledge Trees for Solving RTL Assertion Failures","created":"2025-11-21","cited_by_count":1,"area":null},{"id":"2512.05341","title":"When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generation","created":"2025-12-05","cited_by_count":1,"area":"safety"},{"id":"2603.17296","title":"GUIDE: GenAI Units In Digital Design Education","created":"2026-03-18","cited_by_count":1,"area":null},{"id":"2606.08976","title":"RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models","created":"2026-06-08","cited_by_count":1,"area":"lr"},{"id":"2606.23759","title":"VeriPilot: An LLM-Powered Verilog Debugging Framework","created":"2026-06-22","cited_by_count":1,"area":null},{"id":"2608.27184","title":"LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration","created":"2026-08-27","cited_by_count":1,"area":null},{"id":"2503.11662","title":"Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language","created":"2025-02-14","cited_by_count":0,"area":null},{"id":"2506.05007","title":"QiMeng: Fully Automated Hardware and Software Design for Processor Chip","created":"2025-06-05","cited_by_count":0,"area":null},{"id":"2508.10904","title":"A2H-MAS: An Algorithm-to-HLS Multi-Agent System for Automated and Reliable FPGA Implementation","created":"2025-07-29","cited_by_count":0,"area":"agents"},{"id":"2508.13162","title":"FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design","created":"2025-07-23","cited_by_count":0,"area":null},{"id":"2511.03934","title":"PEFA-AI: Advancing Open-source LLMs for RTL generation using Progressive Error Feedback Agentic-AI","created":"2025-11-06","cited_by_count":0,"area":"agents"},{"id":"2512.06247","title":"DUET: Agentic Design Understanding via Experimentation and Testing","created":"2025-12-06","cited_by_count":0,"area":"agents"},{"id":"2512.21613","title":"AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design","created":"2025-12-25","cited_by_count":0,"area":"agents"},{"id":"2603.05689","title":"SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection","created":"2026-03-05","cited_by_count":0,"area":"rag"},{"id":"2604.19856","title":"ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration","created":"2026-04-21","cited_by_count":0,"area":"agents"},{"id":"2604.23355","title":"LEGO: An LLM Skill-Based Front-End Design Generation Platform","created":"2026-04-25","cited_by_count":0,"area":null},{"id":"2606.04823","title":"R-APS: Compositional Reasoning and In-Context Meta-Learning for Constrained Design via Reflective Adversarial Pareto Search","created":"2026-06-03","cited_by_count":0,"area":"lr"},{"id":"2606.07925","title":"ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards","created":"2026-06-06","cited_by_count":0,"area":null},{"id":"2606.13735","title":"VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation","created":"2026-06-11","cited_by_count":0,"area":null},{"id":"2606.19387","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","created":"2026-06-16","cited_by_count":0,"area":null},{"id":"2607.01609","title":"SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence","created":"2026-07-02","cited_by_count":0,"area":null},{"id":"2607.22761","title":"DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models","created":"2026-07-23","cited_by_count":0,"area":null},{"id":"2608.02915","title":"LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension","created":"2026-08-03","cited_by_count":0,"area":"agents"},{"id":"2608.16934","title":"SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedback","created":"2026-08-09","cited_by_count":0,"area":"agents"},{"id":"2608.26113","title":"PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devices","created":"2026-05-28","cited_by_count":0,"area":null}],"next_cursor":null}