{"total":122,"rows":[{"id":"2308.11432","title":"A Survey on Large Language Model based Autonomous Agents","created":"2023-08-22","cited_by_count":2242,"area":"agents"},{"id":"2311.00176","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","created":"2023-10-31","cited_by_count":174,"area":null},{"id":"2402.03375","title":"BetterV: Controlled Verilog Generation with Discriminative Guidance","created":"2024-02-03","cited_by_count":100,"area":null},{"id":"2405.14918","title":"AnalogCoder: Analog Circuit Design via Training-Free Code Generation","created":"2024-05-23","cited_by_count":84,"area":null},{"id":"2407.16237","title":"OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection","created":"2024-07-23","cited_by_count":56,"area":null},{"id":"2311.15249","title":"Algorithm Evolution Using Large Language Model","created":"2023-11-26","cited_by_count":53,"area":null},{"id":"2407.01910","title":"MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation","created":"2024-07-02","cited_by_count":46,"area":null},{"id":"2507.20280","title":"SciToolAgent: A Knowledge Graph-Driven Scientific Agent for Multi-Tool Integration","created":"2025-07-27","cited_by_count":43,"area":"agents"},{"id":"2501.09655","title":"A Survey of Research in Large Language Models for Electronic Design Automation","created":"2025-01-16","cited_by_count":41,"area":null},{"id":"2401.12224","title":"LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation","created":"2023-12-28","cited_by_count":40,"area":null},{"id":"2503.00205","title":"AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies","created":"2025-02-28","cited_by_count":37,"area":null},{"id":"2508.17281","title":"From Language to Action: A Review of Large Language Models as Autonomous Agents and Tool Users","created":"2025-08-24","cited_by_count":32,"area":"agents"},{"id":"2409.11414","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","created":"2024-09-04","cited_by_count":31,"area":null},{"id":"2310.12541","title":"Large Language Model for Multi-objective Evolutionary Optimization","created":"2023-10-19","cited_by_count":29,"area":null},{"id":"2407.15353","title":"Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA","created":"2024-07-22","cited_by_count":28,"area":"rag"},{"id":"2409.08087","title":"Securing Large Language Models: Addressing Bias, Misinformation, and Prompt Attacks","created":"2024-09-12","cited_by_count":26,"area":"safety"},{"id":"2405.09045","title":"AMSNet: Netlist Dataset for AMS Circuits","created":"2024-05-15","cited_by_count":25,"area":null},{"id":"2410.21418","title":"Large Language Models for Manufacturing","created":"2024-10-28","cited_by_count":24,"area":null},{"id":"2502.15832","title":"DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model","created":"2025-02-20","cited_by_count":23,"area":null},{"id":"2405.07061","title":"LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust","created":"2024-05-11","cited_by_count":20,"area":null},{"id":"2411.11856","title":"Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback","created":"2024-11-01","cited_by_count":19,"area":null},{"id":"2412.19824","title":"AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models","created":"2024-12-17","cited_by_count":18,"area":null},{"id":"2505.13479","title":"RTL++: Graph-enhanced LLM for RTL Code Generation","created":"2025-05-11","cited_by_count":18,"area":null},{"id":"2406.04379","title":"VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation","created":"2024-06-06","cited_by_count":15,"area":null},{"id":"2411.01492","title":"EEE-Bench: A Comprehensive Multimodal Electrical And Electronics Engineering Benchmark","created":"2024-11-03","cited_by_count":15,"area":"mllm"},{"id":"2411.17569","title":"RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation","created":"2024-11-26","cited_by_count":15,"area":"safety"},{"id":"2508.02518","title":"AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs","created":"2025-08-04","cited_by_count":15,"area":null},{"id":"2311.13148","title":"Towards Responsible Generative AI: A Reference Architecture for Designing Foundation Model based Agents","created":"2023-11-22","cited_by_count":14,"area":"lr"},{"id":"2506.08332","title":"ORFS-agent: Tool-Using Agents for Chip Design Optimization","created":"2025-06-10","cited_by_count":14,"area":"agents"},{"id":"2507.16200","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","created":"2025-07-22","cited_by_count":14,"area":null},{"id":"2405.06676","title":"EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD","created":"2024-05-04","cited_by_count":13,"area":null},{"id":"2406.05250","title":"LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation","created":"2024-06-07","cited_by_count":13,"area":null},{"id":"2412.05393","title":"HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design","created":"2024-12-06","cited_by_count":13,"area":null},{"id":"2504.15659","title":"VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation","created":"2025-04-22","cited_by_count":13,"area":null},{"id":"2503.13572","title":"VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination","created":"2025-03-17","cited_by_count":12,"area":null},{"id":"2506.02089","title":"SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design","created":"2025-06-02","cited_by_count":12,"area":"safety"},{"id":"2407.08473","title":"Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation","created":"2024-07-11","cited_by_count":11,"area":null},{"id":"2503.13116","title":"VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding","created":"2025-03-17","cited_by_count":11,"area":null},{"id":"2408.06849","title":"Causal Agent based on Large Language Model","created":"2024-08-13","cited_by_count":10,"area":"agents"},{"id":"2410.20553","title":"SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidance","created":"2024-10-27","cited_by_count":10,"area":null},{"id":"2410.23299","title":"FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware","created":"2024-10-15","cited_by_count":10,"area":null},{"id":"2504.09260","title":"NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph","created":"2025-04-12","cited_by_count":9,"area":null},{"id":"2507.19570","title":"MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization","created":"2025-07-25","cited_by_count":9,"area":"agents"},{"id":"2502.12732","title":"Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment","created":"2025-02-18","cited_by_count":8,"area":null},{"id":"2406.10903","title":"New Solutions on LLM Acceleration, Optimization, and Application","created":"2024-06-16","cited_by_count":7,"area":null},{"id":"2408.16018","title":"SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection","created":"2024-08-25","cited_by_count":7,"area":null},{"id":"2411.03471","title":"MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs","created":"2024-11-05","cited_by_count":7,"area":"lr"},{"id":"2505.22086","title":"iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs","created":"2025-05-28","cited_by_count":7,"area":null},{"id":"2508.14123","title":"AI Agents for Photonic Integrated Circuit Design Automation","created":"2025-08-18","cited_by_count":7,"area":"agents"},{"id":"2412.19819","title":"ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation","created":"2024-12-15","cited_by_count":6,"area":null},{"id":"2507.19525","title":"MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs","created":"2025-07-20","cited_by_count":6,"area":"mllm"},{"id":"2508.01012","title":"AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agents","created":"2025-08-01","cited_by_count":6,"area":"agents"},{"id":"2502.03159","title":"PICBench: Benchmarking LLMs for Photonic Integrated Circuits Design","created":"2025-02-05","cited_by_count":5,"area":null},{"id":"2507.02226","title":"DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs","created":"2025-07-03","cited_by_count":5,"area":null},{"id":"2510.15899","title":"LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models","created":"2025-09-10","cited_by_count":5,"area":null},{"id":"2512.04129","title":"Don't Trust Your Upstream: Exploiting LLM Multi-Agent System via Topology-Guided Adversarial Propagation","created":"2025-12-03","cited_by_count":5,"area":"agents"},{"id":"2512.11611","title":"Using GUI Agent for Electronic Design Automation","created":"2025-12-12","cited_by_count":5,"area":"agents"},{"id":"2601.13864","title":"HardSecBench: Benchmarking the Security Awareness of LLMs for Hardware Code Generation","created":"2026-01-20","cited_by_count":5,"area":null},{"id":"2407.02960","title":"ObfuscaTune: Obfuscated Offsite Fine-tuning and Inference of Proprietary LLMs on Private Datasets","created":"2024-07-03","cited_by_count":4,"area":null},{"id":"2410.03845","title":"ORAssistant: A Custom RAG-based Conversational Assistant for OpenROAD","created":"2024-10-04","cited_by_count":4,"area":null},{"id":"2411.00843","title":"The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation","created":"2024-10-30","cited_by_count":3,"area":null},{"id":"2509.20182","title":"Automated Multi-Agent Workflows for RTL Design","created":"2025-09-24","cited_by_count":3,"area":"agents"},{"id":"2601.19747","title":"Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation","created":"2026-01-27","cited_by_count":3,"area":"agents"},{"id":"2311.16267","title":"Novel Preprocessing Technique for Data Embedding in Engineering Code Generation Using Large Language Model","created":"2023-11-27","cited_by_count":2,"area":null},{"id":"2408.12775","title":"Intelligent OPC Engineer Assistant for Semiconductor Manufacturing","created":"2024-08-23","cited_by_count":2,"area":null},{"id":"2503.05951","title":"TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator","created":"2025-03-07","cited_by_count":2,"area":null},{"id":"2503.22473","title":"WorkTeam: Constructing Workflows from Natural Language with Multi-Agents","created":"2025-03-28","cited_by_count":2,"area":"agents"},{"id":"2505.13994","title":"Divide by Question, Conquer by Agent: SPLIT-RAG with Question-Driven Graph Partitioning","created":"2025-05-20","cited_by_count":2,"area":"rag"},{"id":"2506.06500","title":"Improving LLM-Powered EDA Assistants with RAFT","created":"2025-06-06","cited_by_count":2,"area":"rag"},{"id":"2507.23035","title":"OASIS: Outlier-Aware LUT-Based GEMM with Dual-Side Quantization for LLM Inference Acceleration","created":"2025-07-30","cited_by_count":2,"area":"inference"},{"id":"2508.13156","title":"EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code","created":"2025-06-26","cited_by_count":2,"area":null},{"id":"2508.18554","title":"SchemaCoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting","created":"2025-08-25","cited_by_count":2,"area":null},{"id":"2512.23742","title":"AgenticTCAD: A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device Optimization","created":"2025-12-26","cited_by_count":2,"area":"agents"},{"id":"2604.27238","title":"SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation","created":"2026-04-29","cited_by_count":2,"area":"safety"},{"id":"2605.06936","title":"Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing","created":"2026-05-07","cited_by_count":2,"area":"agents"},{"id":"2407.12576","title":"IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA","created":"2024-07-17","cited_by_count":1,"area":null},{"id":"2407.12749","title":"ChipXplore: Natural Language Exploration of Hardware Designs and Libraries","created":"2024-07-17","cited_by_count":1,"area":null},{"id":"2504.05180","title":"BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks","created":"2025-04-07","cited_by_count":1,"area":null},{"id":"2504.09485","title":"GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment","created":"2025-04-13","cited_by_count":1,"area":"lr"},{"id":"2505.09610","title":"Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors","created":"2025-05-14","cited_by_count":1,"area":null},{"id":"2508.05675","title":"Principle-Guided Verilog Optimization: IP-Safe Knowledge Transfer via Local-Cloud Collaboration","created":"2025-08-05","cited_by_count":1,"area":null},{"id":"2508.14053","title":"MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging","created":"2025-08-08","cited_by_count":1,"area":"agents"},{"id":"2508.19087","title":"APT-LLM: Exploiting Arbitrary-Precision Tensor Core Computing for LLM Acceleration","created":"2025-08-26","cited_by_count":1,"area":null},{"id":"2510.20641","title":"Integrating Machine Learning into Belief-Desire-Intention Agents: Current Advances and Open Challenges","created":"2025-10-23","cited_by_count":1,"area":null},{"id":"2512.05341","title":"When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generation","created":"2025-12-05","cited_by_count":1,"area":"safety"},{"id":"2603.25243","title":"FluxEDA: A Unified Execution Infrastructure for Stateful Agentic EDA","created":"2026-03-26","cited_by_count":1,"area":"agents"},{"id":"2605.02592","title":"Foundation-Model-Based Agents in Industrial Automation: Purposes, Capabilities, and Open Challenges","created":"2026-05-04","cited_by_count":1,"area":"agents"},{"id":"2607.03701","title":"SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows","created":"2026-07-04","cited_by_count":1,"area":null},{"id":"2607.18536","title":"MAGE: Human-Like Macro Placement via Agentic Multimodal Reasoning","created":"2026-07-20","cited_by_count":1,"area":"lr"},{"id":"2607.20019","title":"EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair","created":"2026-07-22","cited_by_count":1,"area":null},{"id":"2608.03738","title":"AgenticECO: An Agentic Framework for ECO on 3D Integrated Circuits","created":"2026-08-04","cited_by_count":1,"area":null},{"id":"2608.27184","title":"LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration","created":"2026-08-27","cited_by_count":1,"area":null},{"id":"2404.08850","title":"Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance","created":"2024-04-12","cited_by_count":0,"area":null},{"id":"2502.16540","title":"D2S-FLOW: Automated Parameter Extraction from Datasheets for SPICE Model Generation Using Large Language Models","created":"2025-02-23","cited_by_count":0,"area":null},{"id":"2506.05007","title":"QiMeng: Fully Automated Hardware and Software Design for Processor Chip","created":"2025-06-05","cited_by_count":0,"area":null},{"id":"2508.13162","title":"FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design","created":"2025-07-23","cited_by_count":0,"area":null},{"id":"2511.05823","title":"AiEDA: An Open-Source AI-Aided Design Library for Design-to-Vector","created":"2025-11-08","cited_by_count":0,"area":null},{"id":"2512.21613","title":"AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design","created":"2025-12-25","cited_by_count":0,"area":"agents"},{"id":"2603.08745","title":"ChatNeuroSim: An LLM Agent Framework for Automated Compute-in-Memory Accelerator Deployment and Optimization","created":"2026-03-04","cited_by_count":0,"area":"agents"},{"id":"2604.21952","title":"Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models","created":"2026-04-23","cited_by_count":0,"area":null}],"next_cursor":"100"}