{"total":137,"rows":[{"id":"2308.10620","title":"Large Language Models for Software Engineering: A Systematic Literature Review","created":"2023-08-21","cited_by_count":399,"area":null},{"id":"2405.14918","title":"AnalogCoder: Analog Circuit Design via Training-Free Code Generation","created":"2024-05-23","cited_by_count":84,"area":null},{"id":"2311.07989","title":"Unifying the Perspectives of NLP and Software Engineering: A Survey on Language Models for Code","created":"2023-11-14","cited_by_count":62,"area":null},{"id":"2407.01910","title":"MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation","created":"2024-07-02","cited_by_count":46,"area":null},{"id":"2408.11053","title":"Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation","created":"2024-08-20","cited_by_count":45,"area":null},{"id":"2501.09655","title":"A Survey of Research in Large Language Models for Electronic Design Automation","created":"2025-01-16","cited_by_count":41,"area":null},{"id":"2401.12224","title":"LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation","created":"2023-12-28","cited_by_count":40,"area":null},{"id":"2503.00205","title":"AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies","created":"2025-02-28","cited_by_count":37,"area":null},{"id":"2409.11414","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","created":"2024-09-04","cited_by_count":31,"area":null},{"id":"2403.11671","title":"HDLdebugger: Streamlining HDL debugging with Large Language Models","created":"2024-03-18","cited_by_count":26,"area":null},{"id":"2405.17378","title":"RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects","created":"2024-05-27","cited_by_count":26,"area":null},{"id":"2312.14950","title":"TypeFly: Flying Drones with Large Language Model","created":"2023-12-08","cited_by_count":23,"area":null},{"id":"2502.15832","title":"DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model","created":"2025-02-20","cited_by_count":23,"area":null},{"id":"2310.06046","title":"LLM for SoC Security: A Paradigm Shift","created":"2023-10-09","cited_by_count":22,"area":null},{"id":"2401.05443","title":"LLM4PLC: Harnessing Large Language Models for Verifiable Programming of PLCs in Industrial Control Systems","created":"2024-01-08","cited_by_count":21,"area":null},{"id":"2502.18297","title":"DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis","created":"2025-02-25","cited_by_count":21,"area":null},{"id":"2405.07061","title":"LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust","created":"2024-05-11","cited_by_count":20,"area":null},{"id":"2404.08806","title":"CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation","created":"2024-04-12","cited_by_count":19,"area":null},{"id":"2505.13479","title":"RTL++: Graph-enhanced LLM for RTL Code Generation","created":"2025-05-11","cited_by_count":18,"area":null},{"id":"2406.04373","title":"VerilogReader: LLM-Aided Hardware Test Generation","created":"2024-06-03","cited_by_count":17,"area":null},{"id":"2411.13560","title":"AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAG","created":"2024-11-07","cited_by_count":16,"area":null},{"id":"2406.04379","title":"VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation","created":"2024-06-06","cited_by_count":15,"area":null},{"id":"2407.18271","title":"Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning","created":"2024-07-21","cited_by_count":15,"area":null},{"id":"2409.11411","title":"AIvril: AI-Driven RTL Generation With Verification In-The-Loop","created":"2024-09-03","cited_by_count":15,"area":null},{"id":"2505.20302","title":"VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification","created":"2025-05-16","cited_by_count":15,"area":null},{"id":"2508.02518","title":"AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs","created":"2025-08-04","cited_by_count":15,"area":null},{"id":"2406.05250","title":"LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation","created":"2024-06-07","cited_by_count":13,"area":null},{"id":"2412.20545","title":"The Impact of Prompt Programming on Function-Level Code Generation","created":"2024-12-29","cited_by_count":13,"area":null},{"id":"2504.15659","title":"VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation","created":"2025-04-22","cited_by_count":13,"area":null},{"id":"2503.13572","title":"VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination","created":"2025-03-17","cited_by_count":12,"area":null},{"id":"2407.08473","title":"Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation","created":"2024-07-11","cited_by_count":11,"area":null},{"id":"2503.13116","title":"VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding","created":"2025-03-17","cited_by_count":11,"area":null},{"id":"2402.01728","title":"Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge","created":"2024-01-27","cited_by_count":10,"area":null},{"id":"2410.20553","title":"SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidance","created":"2024-10-27","cited_by_count":10,"area":null},{"id":"2410.23299","title":"FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware","created":"2024-10-15","cited_by_count":10,"area":null},{"id":"2503.08923","title":"Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset","created":"2025-03-11","cited_by_count":10,"area":null},{"id":"2504.12268","title":"HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks","created":"2025-04-16","cited_by_count":10,"area":null},{"id":"2506.15697","title":"DeepRTL2: A Versatile Model for RTL-Related Tasks","created":"2025-05-28","cited_by_count":10,"area":null},{"id":"2504.01986","title":"TuRTLe: A Unified Evaluation of LLMs for RTL Generation","created":"2025-03-31","cited_by_count":9,"area":null},{"id":"2504.19959","title":"From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification","created":"2025-04-28","cited_by_count":9,"area":null},{"id":"2405.02326","title":"Evaluating LLMs for Hardware Design and Test","created":"2024-04-23","cited_by_count":8,"area":null},{"id":"2504.21187","title":"LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning","created":"2025-04-29","cited_by_count":8,"area":null},{"id":"2507.13369","title":"VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation","created":"2025-07-09","cited_by_count":8,"area":null},{"id":"2508.05266","title":"Understanding and Mitigating Errors of LLM-Generated RTL Code","created":"2025-08-07","cited_by_count":8,"area":null},{"id":"2512.00020","title":"Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead","created":"2025-10-29","cited_by_count":8,"area":null},{"id":"2601.21448","title":"ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design","created":"2026-01-29","cited_by_count":8,"area":null},{"id":"2406.10903","title":"New Solutions on LLM Acceleration, Optimization, and Application","created":"2024-06-16","cited_by_count":7,"area":null},{"id":"2408.16018","title":"SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection","created":"2024-08-25","cited_by_count":7,"area":null},{"id":"2411.16111","title":"LLMPirate: LLMs for Black-box Hardware IP Piracy","created":"2024-11-25","cited_by_count":7,"area":null},{"id":"2505.22086","title":"iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs","created":"2025-05-28","cited_by_count":7,"area":null},{"id":"2408.10428","title":"Are LLMs Any Good for High-Level Synthesis?","created":"2024-08-19","cited_by_count":6,"area":null},{"id":"2505.19734","title":"ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection","created":"2025-05-26","cited_by_count":6,"area":null},{"id":"2507.12308","title":"Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization","created":"2025-07-16","cited_by_count":6,"area":null},{"id":"2401.08683","title":"Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Models","created":"2024-01-12","cited_by_count":5,"area":null},{"id":"2402.09615","title":"API Pack: A Massive Multi-Programming Language Dataset for API Call Generation","created":"2024-02-14","cited_by_count":5,"area":null},{"id":"2403.13838","title":"Circuit Transformer: A Transformer That Preserves Logical Equivalence","created":"2024-03-14","cited_by_count":5,"area":null},{"id":"2503.08823","title":"ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awareness","created":"2025-03-11","cited_by_count":5,"area":null},{"id":"2507.02226","title":"DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs","created":"2025-07-03","cited_by_count":5,"area":null},{"id":"2510.15899","title":"LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models","created":"2025-09-10","cited_by_count":5,"area":null},{"id":"2310.09690","title":"Configuration Validation with Large Language Models","created":"2023-10-15","cited_by_count":4,"area":null},{"id":"2411.15442","title":"Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting","created":"2024-11-23","cited_by_count":4,"area":null},{"id":"2510.19296","title":"QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation","created":"2025-10-22","cited_by_count":4,"area":null},{"id":"2510.21407","title":"REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models","created":"2025-10-24","cited_by_count":4,"area":null},{"id":"2601.22114","title":"SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence","created":"2026-01-29","cited_by_count":4,"area":null},{"id":"2404.07235","title":"LLM-aided explanations of EDA synthesis errors","created":"2024-04-07","cited_by_count":3,"area":null},{"id":"2407.18326","title":"Classification-Based Automatic HDL Code Generation Using LLMs","created":"2024-07-04","cited_by_count":3,"area":null},{"id":"2411.00843","title":"The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation","created":"2024-10-30","cited_by_count":3,"area":null},{"id":"2506.07239","title":"VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code","created":"2025-06-08","cited_by_count":3,"area":null},{"id":"2508.01237","title":"SketchAgent: Generating Structured Diagrams from Hand-Drawn Sketches","created":"2025-08-02","cited_by_count":3,"area":null},{"id":"2508.20030","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","created":"2025-08-27","cited_by_count":3,"area":null},{"id":"2510.14756","title":"Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code","created":"2025-10-16","cited_by_count":3,"area":null},{"id":"2511.16395","title":"CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference","created":"2025-11-20","cited_by_count":3,"area":null},{"id":"2603.08718","title":"CktEvo: Repository-Level RTL Code Benchmark for Design Evolution","created":"2026-02-10","cited_by_count":3,"area":null},{"id":"2607.13292","title":"Theory-Level Autoformalization: From Isolated Statements to Unified Formal Knowledge Bases","created":"2026-07-14","cited_by_count":3,"area":null},{"id":"2311.16267","title":"Novel Preprocessing Technique for Data Embedding in Engineering Code Generation Using Large Language Model","created":"2023-11-27","cited_by_count":2,"area":null},{"id":"2409.15228","title":"A Comprehensive Framework for Evaluating API-oriented Code Generation in Large Language Models","created":"2024-09-23","cited_by_count":2,"area":null},{"id":"2503.05951","title":"TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator","created":"2025-03-07","cited_by_count":2,"area":null},{"id":"2505.06096","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","created":"2025-05-09","cited_by_count":2,"area":null},{"id":"2507.10639","title":"Evaluating LLM-based Workflows for Switched-Mode Power Supply Design","created":"2025-07-14","cited_by_count":2,"area":null},{"id":"2508.12910","title":"SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip","created":"2025-08-18","cited_by_count":2,"area":null},{"id":"2508.13156","title":"EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code","created":"2025-06-26","cited_by_count":2,"area":null},{"id":"2511.12033","title":"EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation","created":"2025-11-15","cited_by_count":2,"area":null},{"id":"2604.27643","title":"HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs","created":"2026-04-30","cited_by_count":2,"area":null},{"id":"2605.24144","title":"EVA: Accelerating LLM Decoding via an Efficient Vector Quantization Architecture","created":"2026-05-22","cited_by_count":2,"area":null},{"id":"2405.01419","title":"Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT","created":"2024-05-02","cited_by_count":1,"area":null},{"id":"2405.02329","title":"Digital ASIC Design with Ongoing LLMs: Strategies and Prospects","created":"2024-04-25","cited_by_count":1,"area":null},{"id":"2407.18423","title":"HDL-GPT: High-Quality HDL is All You Need","created":"2024-07-25","cited_by_count":1,"area":null},{"id":"2505.09610","title":"Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors","created":"2025-05-14","cited_by_count":1,"area":null},{"id":"2506.07945","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","created":"2025-06-09","cited_by_count":1,"area":null},{"id":"2507.16203","title":"SVAgent: AI Agent for Hardware Security Verification Assertion","created":"2025-07-22","cited_by_count":1,"area":null},{"id":"2507.16808","title":"Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosis","created":"2025-07-22","cited_by_count":1,"area":null},{"id":"2508.05675","title":"Principle-Guided Verilog Optimization: IP-Safe Knowledge Transfer via Local-Cloud Collaboration","created":"2025-08-05","cited_by_count":1,"area":null},{"id":"2508.18730","title":"Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning","created":"2025-08-26","cited_by_count":1,"area":null},{"id":"2510.08664","title":"Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware","created":"2025-10-09","cited_by_count":1,"area":null},{"id":"2510.16022","title":"Breaking Memorization Barriers in LLM Code Fine-Tuning via Information Bottleneck for Improved Generalization","created":"2025-10-15","cited_by_count":1,"area":null},{"id":"2511.06067","title":"Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework","created":"2025-11-08","cited_by_count":1,"area":null},{"id":"2602.00704","title":"QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generation","created":"2026-01-31","cited_by_count":1,"area":null},{"id":"2603.08715","title":"VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation","created":"2026-02-04","cited_by_count":1,"area":null},{"id":"2604.17102","title":"Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation","created":"2026-04-18","cited_by_count":1,"area":null},{"id":"2604.23602","title":"TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog","created":"2026-04-26","cited_by_count":1,"area":null}],"next_cursor":"100"}