{"total":33,"rows":[{"id":"2405.14918","title":"AnalogCoder: Analog Circuit Design via Training-Free Code Generation","created":"2024-05-23","cited_by_count":84,"area":null},{"id":"2306.16844","title":"Macro Placement by Wire-Mask-Guided Black-Box Optimization","created":"2023-06-29","cited_by_count":23,"area":null},{"id":"2412.19824","title":"AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models","created":"2024-12-17","cited_by_count":18,"area":null},{"id":"2407.15026","title":"Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms","created":"2024-07-03","cited_by_count":14,"area":null},{"id":"2406.05250","title":"LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation","created":"2024-06-07","cited_by_count":13,"area":null},{"id":"2402.01728","title":"Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge","created":"2024-01-27","cited_by_count":10,"area":null},{"id":"2405.06758","title":"Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs","created":"2024-05-10","cited_by_count":9,"area":null},{"id":"2407.07346","title":"INSIGHT: Universal Neural Simulator for Analog Circuits Harnessing Autoregressive Transformers","created":"2024-07-10","cited_by_count":8,"area":null},{"id":"2309.03208","title":"A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design","created":"2023-08-22","cited_by_count":6,"area":null},{"id":"2504.17801","title":"Evolution of Optimization Algorithms for Global Placement via Large Language Models","created":"2025-04-18","cited_by_count":6,"area":null},{"id":"2403.00012","title":"PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling","created":"2024-02-27","cited_by_count":5,"area":null},{"id":"2411.10053","title":"That Chip Has Sailed: A Critique of Unfounded Skepticism Around AI for Chip Design","created":"2024-11-15","cited_by_count":5,"area":null},{"id":"2411.15212","title":"Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning","created":"2024-11-20","cited_by_count":5,"area":null},{"id":"2510.23472","title":"BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement","created":"2025-10-27","cited_by_count":5,"area":null},{"id":"2405.14790","title":"DIDI: Diffusion-Guided Diversity for Offline Behavioral Generation","created":"2024-05-23","cited_by_count":4,"area":null},{"id":"2405.05480","title":"FloorSet -- a VLSI Floorplanning Dataset with Design Constraints of Real-World SoCs","created":"2024-05-09","cited_by_count":3,"area":null},{"id":"2406.02651","title":"RoutePlacer: An End-to-End Routability-Aware Placer with Graph Neural Network","created":"2024-06-04","cited_by_count":1,"area":null},{"id":"2603.28733","title":"See it to Place it: Evolving Macro Placements with Vision-Language Models","created":"2026-03-30","cited_by_count":1,"area":null},{"id":"2605.16451","title":"Physics-Guided Geometric Diffusion for Macro Placement Generation","created":"2026-05-15","cited_by_count":1,"area":null},{"id":"2404.13061","title":"FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning","created":"2024-04-11","cited_by_count":0,"area":null},{"id":"2406.10538","title":"Addressing Large Action Spaces in 3D Floorplanning via Spatial Generalization","created":"2024-06-15","cited_by_count":0,"area":null},{"id":"2411.02933","title":"P-MOSS: Scheduling Main-Memory Indexes Over NUMA Servers Using Next Token Prediction","created":"2024-11-05","cited_by_count":0,"area":null},{"id":"2501.05667","title":"TransPlace: Transferable Circuit Global Placement via Graph Neural Network","created":"2025-01-10","cited_by_count":0,"area":null},{"id":"2503.03040","title":"SAGE: Steering Dialog Generation with Future-Aware State-Action Augmentation","created":"2025-03-04","cited_by_count":0,"area":null},{"id":"2510.15387","title":"Advancing Routing-Awareness in Analog ICs Floorplanning","created":"2025-10-17","cited_by_count":0,"area":null},{"id":"2511.08054","title":"Re$^{\\text{2}}$MaP: Macro Placement by Recursively Prototyping and Packing Tree-based Relocating","created":"2025-11-11","cited_by_count":0,"area":null},{"id":"2601.22476","title":"RulePlanner: All-in-One Reinforcement Learner for Unifying Design Rules in 3D Floorplanning","created":"2026-01-30","cited_by_count":0,"area":null},{"id":"2602.11187","title":"TDPNavigator-Placer: Thermal- and Wirelength-Aware Chiplet Placement in 2.5D Systems Through Multi-Agent Reinforcement Learning","created":"2026-01-30","cited_by_count":0,"area":null},{"id":"2605.08291","title":"Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation","created":"2026-05-08","cited_by_count":0,"area":null},{"id":"2605.10547","title":"PhysEDA: Physics-Aware Learning Framework for Efficient EDA With Manhattan Distance Decay","created":"2026-05-11","cited_by_count":0,"area":null},{"id":"2608.13790","title":"PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization","created":"2026-08-13","cited_by_count":0,"area":null},{"id":"2609.21263","title":"PlaceReasoner-Beta: Reasoning-Driven Macro Placement and Benchmarking","created":"2026-09-18","cited_by_count":0,"area":null},{"id":"2609.33106","title":"CARVE: Breaking Data Barriers in Chip Placement by Harnessing Reusable Expertise","created":"2026-09-27","cited_by_count":0,"area":null}],"next_cursor":null}