{"total":75,"rows":[{"id":"2309.07544","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","created":"2023-09-14","cited_by_count":252,"area":null},{"id":"2308.00708","title":"VeriGen: A Large Language Model for Verilog Code Generation","created":"2023-07-28","cited_by_count":200,"area":null},{"id":"2308.05345","title":"RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model","created":"2023-08-10","cited_by_count":148,"area":null},{"id":"2405.14918","title":"AnalogCoder: Analog Circuit Design via Training-Free Code Generation","created":"2024-05-23","cited_by_count":84,"area":null},{"id":"2407.16237","title":"OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection","created":"2024-07-23","cited_by_count":56,"area":null},{"id":"2407.01910","title":"MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation","created":"2024-07-02","cited_by_count":46,"area":null},{"id":"2408.11053","title":"Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation","created":"2024-08-20","cited_by_count":45,"area":null},{"id":"2501.09655","title":"A Survey of Research in Large Language Models for Electronic Design Automation","created":"2025-01-16","cited_by_count":41,"area":null},{"id":"2401.12224","title":"LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation","created":"2023-12-28","cited_by_count":40,"area":null},{"id":"2407.10424","title":"CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization","created":"2024-07-15","cited_by_count":38,"area":null},{"id":"2503.00205","title":"AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies","created":"2025-02-28","cited_by_count":37,"area":null},{"id":"2407.18333","title":"AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs","created":"2024-07-21","cited_by_count":36,"area":null},{"id":"2502.15832","title":"DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model","created":"2025-02-20","cited_by_count":23,"area":null},{"id":"2310.06046","title":"LLM for SoC Security: A Paradigm Shift","created":"2023-10-09","cited_by_count":22,"area":null},{"id":"2405.07061","title":"LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust","created":"2024-05-11","cited_by_count":20,"area":null},{"id":"2411.11856","title":"Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback","created":"2024-11-01","cited_by_count":19,"area":null},{"id":"2412.06947","title":"PyraNet: A Multi-Layered Hierarchical Dataset for Verilog","created":"2024-12-09","cited_by_count":19,"area":null},{"id":"2402.00093","title":"ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation","created":"2024-01-31","cited_by_count":16,"area":null},{"id":"2406.04379","title":"VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation","created":"2024-06-06","cited_by_count":15,"area":null},{"id":"2407.18271","title":"Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning","created":"2024-07-21","cited_by_count":15,"area":null},{"id":"2409.11411","title":"AIvril: AI-Driven RTL Generation With Verification In-The-Loop","created":"2024-09-03","cited_by_count":15,"area":null},{"id":"2508.02518","title":"AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs","created":"2025-08-04","cited_by_count":15,"area":null},{"id":"2507.16200","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","created":"2025-07-22","cited_by_count":14,"area":null},{"id":"2405.06676","title":"EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD","created":"2024-05-04","cited_by_count":13,"area":null},{"id":"2412.05393","title":"HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design","created":"2024-12-06","cited_by_count":13,"area":null},{"id":"2503.13572","title":"VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination","created":"2025-03-17","cited_by_count":12,"area":null},{"id":"2306.06923","title":"On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators","created":"2023-06-12","cited_by_count":11,"area":null},{"id":"2403.16750","title":"All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification","created":"2024-03-25","cited_by_count":11,"area":null},{"id":"2407.08473","title":"Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation","created":"2024-07-11","cited_by_count":11,"area":null},{"id":"2503.13116","title":"VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding","created":"2025-03-17","cited_by_count":11,"area":null},{"id":"2410.20553","title":"SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidance","created":"2024-10-27","cited_by_count":10,"area":null},{"id":"2407.12022","title":"ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generation","created":"2024-06-28","cited_by_count":9,"area":null},{"id":"2504.01986","title":"TuRTLe: A Unified Evaluation of LLMs for RTL Generation","created":"2025-03-31","cited_by_count":9,"area":null},{"id":"2504.19959","title":"From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification","created":"2025-04-28","cited_by_count":9,"area":null},{"id":"2509.04905","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","created":"2025-09-05","cited_by_count":9,"area":null},{"id":"2507.13369","title":"VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation","created":"2025-07-09","cited_by_count":8,"area":null},{"id":"2512.00020","title":"Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead","created":"2025-10-29","cited_by_count":8,"area":null},{"id":"2506.00005","title":"Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form","created":"2025-05-07","cited_by_count":7,"area":null},{"id":"2405.16072","title":"SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generation","created":"2024-05-25","cited_by_count":6,"area":null},{"id":"2408.10428","title":"Are LLMs Any Good for High-Level Synthesis?","created":"2024-08-19","cited_by_count":6,"area":null},{"id":"2505.19734","title":"ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection","created":"2025-05-26","cited_by_count":6,"area":null},{"id":"2401.08683","title":"Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Models","created":"2024-01-12","cited_by_count":5,"area":null},{"id":"2505.22878","title":"BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection","created":"2025-05-28","cited_by_count":5,"area":null},{"id":"2507.02226","title":"DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs","created":"2025-07-03","cited_by_count":5,"area":null},{"id":"2411.13802","title":"SemiKong: Curating, Training, and Evaluating A Semiconductor Industry-Specific Large Language Model","created":"2024-11-21","cited_by_count":4,"area":null},{"id":"2604.15001","title":"COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation","created":"2026-04-16","cited_by_count":3,"area":null},{"id":"2503.05951","title":"TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator","created":"2025-03-07","cited_by_count":2,"area":null},{"id":"2505.06096","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","created":"2025-05-09","cited_by_count":2,"area":null},{"id":"2506.04544","title":"hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation","created":"2025-06-05","cited_by_count":2,"area":null},{"id":"2507.10639","title":"Evaluating LLM-based Workflows for Switched-Mode Power Supply Design","created":"2025-07-14","cited_by_count":2,"area":null},{"id":"2508.13156","title":"EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code","created":"2025-06-26","cited_by_count":2,"area":null},{"id":"2511.12033","title":"EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation","created":"2025-11-15","cited_by_count":2,"area":null},{"id":"2604.27643","title":"HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs","created":"2026-04-30","cited_by_count":2,"area":null},{"id":"2402.10920","title":"Designing Silicon Brains using LLM: Leveraging ChatGPT for Automated Description of a Spiking Neuron Array","created":"2024-01-25","cited_by_count":1,"area":null},{"id":"2504.05180","title":"BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks","created":"2025-04-07","cited_by_count":1,"area":null},{"id":"2505.09610","title":"Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors","created":"2025-05-14","cited_by_count":1,"area":null},{"id":"2506.07945","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","created":"2025-06-09","cited_by_count":1,"area":null},{"id":"2601.08856","title":"LAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns","created":"2026-01-06","cited_by_count":1,"area":null},{"id":"2601.14541","title":"Report for NSF Workshop on AI for Electronic Design Automation","created":"2026-01-20","cited_by_count":1,"area":null},{"id":"2606.01188","title":"pcbGPT: Automatic PCB Schematic Synthesis from Natural Language Requirements","created":"2026-05-31","cited_by_count":1,"area":null},{"id":"2608.27184","title":"LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration","created":"2026-08-27","cited_by_count":1,"area":null},{"id":"2404.08850","title":"Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance","created":"2024-04-12","cited_by_count":0,"area":null},{"id":"2503.11662","title":"Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language","created":"2025-02-14","cited_by_count":0,"area":null},{"id":"2504.01981","title":"NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI","created":"2025-03-28","cited_by_count":0,"area":null},{"id":"2506.00002","title":"Advancing AI-assisted Hardware Design with Hierarchical Decentralized Training and Personalized Inference-Time Optimization","created":"2025-04-21","cited_by_count":0,"area":null},{"id":"2506.05007","title":"QiMeng: Fully Automated Hardware and Software Design for Processor Chip","created":"2025-06-05","cited_by_count":0,"area":null},{"id":"2508.13162","title":"FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design","created":"2025-07-23","cited_by_count":0,"area":null},{"id":"2603.25769","title":"IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution","created":"2026-03-26","cited_by_count":0,"area":null},{"id":"2604.18445","title":"AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning","created":"2026-04-20","cited_by_count":0,"area":null},{"id":"2605.07782","title":"CktFormalizer: Autoformalization of Natural Language into Circuit Representations","created":"2026-05-08","cited_by_count":0,"area":null},{"id":"2605.26498","title":"Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation","created":"2026-05-26","cited_by_count":0,"area":null},{"id":"2607.01609","title":"SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence","created":"2026-07-02","cited_by_count":0,"area":null},{"id":"2608.26113","title":"PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devices","created":"2026-05-28","cited_by_count":0,"area":null},{"id":"2609.34976","title":"Inspector: Conversational and Lightweight Analyzer of Analog Circuit Layouts Using LLM and CNNs","created":"2026-09-28","cited_by_count":0,"area":null},{"id":"2609.35035","title":"THEIA: A Multimodal Dataset and Benchmark for Vision-Language Analysis of Layout","created":"2026-09-28","cited_by_count":0,"area":null}],"next_cursor":null}