{"total":23,"rows":[{"id":"2207.05984","title":"Unsupervised Learning for Combinatorial Optimization with Principled Objective Relaxation","created":"2022-07-13","cited_by_count":32,"area":null},{"id":"2406.09606","title":"Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis","created":"2024-06-13","cited_by_count":10,"area":null},{"id":"2209.03465","title":"TAG: Learning Circuit Spatial Embedding From Layouts","created":"2022-09-07","cited_by_count":9,"area":null},{"id":"2407.20912","title":"What Are Good Positional Encodings for Directed Graphs?","created":"2024-07-30","cited_by_count":8,"area":null},{"id":"2504.21187","title":"LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning","created":"2025-04-29","cited_by_count":8,"area":null},{"id":"2201.08455","title":"LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models","created":"2022-01-20","cited_by_count":7,"area":null},{"id":"2505.22086","title":"iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs","created":"2025-05-28","cited_by_count":7,"area":null},{"id":"2311.05722","title":"Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs","created":"2023-11-09","cited_by_count":5,"area":null},{"id":"2401.08696","title":"Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs","created":"2024-01-14","cited_by_count":5,"area":null},{"id":"2302.10977","title":"HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis","created":"2023-02-17","cited_by_count":4,"area":null},{"id":"2408.13270","title":"Efficient Task Transfer for HLS DSE","created":"2024-08-16","cited_by_count":4,"area":null},{"id":"2211.16495","title":"Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs","created":"2022-11-29","cited_by_count":3,"area":null},{"id":"2409.13138","title":"Learning to Compare Hardware Designs for High-Level Synthesis","created":"2024-09-20","cited_by_count":3,"area":null},{"id":"2412.07188","title":"Graph Neural Networks Are More Than Filters: Revisiting and Benchmarking from A Spectral Perspective","created":"2024-12-10","cited_by_count":3,"area":null},{"id":"2511.05615","title":"wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation","created":"2025-11-06","cited_by_count":2,"area":null},{"id":"2204.09579","title":"A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation","created":"2022-04-19","cited_by_count":1,"area":null},{"id":"2410.06460","title":"A Benchmark on Directed Graph Representation Learning in Hardware Designs","created":"2024-10-09","cited_by_count":1,"area":null},{"id":"2507.03255","title":"ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis","created":"2025-07-04","cited_by_count":1,"area":null},{"id":"2502.16203","title":"Machine Learning Framework for Early Power, Performance, and Area Estimation of RTL","created":"2025-02-22","cited_by_count":0,"area":null},{"id":"2509.13735","title":"State Space Models over Directed Graphs","created":"2025-09-17","cited_by_count":0,"area":null},{"id":"2602.03808","title":"Enhancing Imbalanced Node Classification via Curriculum-Guided Feature Learning and Three-Stage Attention Network","created":"2026-02-03","cited_by_count":0,"area":null},{"id":"2605.16138","title":"SNAC-Pack 2.0: Scaled-Out Surrogate Neural Architecture Codesign","created":"2026-05-15","cited_by_count":0,"area":null},{"id":"2610.04657","title":"Path Laplacian Encodings for Directed Graphs","created":"2026-10-03","cited_by_count":0,"area":null}],"next_cursor":null}