{"total":22,"rows":[{"id":"2207.05984","title":"Unsupervised Learning for Combinatorial Optimization with Principled Objective Relaxation","created":"2022-07-13","cited_by_count":32,"area":null},{"id":"2201.06848","title":"High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing","created":"2022-01-18","cited_by_count":26,"area":null},{"id":"2212.11142","title":"BaCO: A Fast and Portable Bayesian Compiler Optimization Framework","created":"2022-12-01","cited_by_count":11,"area":null},{"id":"2405.00820","title":"HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond","created":"2024-05-01","cited_by_count":8,"area":null},{"id":"2504.21187","title":"LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning","created":"2025-04-29","cited_by_count":8,"area":null},{"id":"2201.08455","title":"LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models","created":"2022-01-20","cited_by_count":7,"area":null},{"id":"2311.05722","title":"Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs","created":"2023-11-09","cited_by_count":5,"area":null},{"id":"2211.02052","title":"Theta-Resonance: A Single-Step Reinforcement Learning Method for Design Space Exploration","created":"2022-11-03","cited_by_count":4,"area":null},{"id":"2502.05850","title":"MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration","created":"2025-02-09","cited_by_count":4,"area":null},{"id":"2211.16495","title":"Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs","created":"2022-11-29","cited_by_count":3,"area":null},{"id":"2409.13138","title":"Learning to Compare Hardware Designs for High-Level Synthesis","created":"2024-09-20","cited_by_count":3,"area":null},{"id":"2401.10753","title":"BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation","created":"2024-01-19","cited_by_count":2,"area":null},{"id":"2109.06265","title":"Program-to-Circuit: Exploiting GNNs for Program Representation and Circuit Translation","created":"2021-09-13","cited_by_count":1,"area":null},{"id":"2204.09579","title":"A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation","created":"2022-04-19","cited_by_count":1,"area":null},{"id":"2410.06460","title":"A Benchmark on Directed Graph Representation Learning in Hardware Designs","created":"2024-10-09","cited_by_count":1,"area":null},{"id":"2507.03255","title":"ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis","created":"2025-07-04","cited_by_count":1,"area":null},{"id":"2601.04801","title":"MPM-LLM4DSE: Reaching the Pareto Frontier in HLS with Multimodal Learning and LLM-Driven Exploration","created":"2026-01-08","cited_by_count":1,"area":null},{"id":"2110.04280","title":"Pyxis: An Open-Source Performance Dataset of Sparse Accelerators","created":"2021-10-08","cited_by_count":0,"area":null},{"id":"2111.08848","title":"Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks","created":"2021-11-17","cited_by_count":0,"area":null},{"id":"2501.05667","title":"TransPlace: Transferable Circuit Global Placement via Graph Neural Network","created":"2025-01-10","cited_by_count":0,"area":null},{"id":"2507.18804","title":"Ralts: Robust Aggregation for Enhancing Graph Neural Network Resilience on Bit-flip Errors","created":"2025-07-24","cited_by_count":0,"area":null},{"id":"2610.00106","title":"SyntheticHLS: Building Diverse Synthetic High-Level Synthesis Datasets using LLMs","created":"2026-09-09","cited_by_count":0,"area":null}],"next_cursor":null}