{"total":69,"rows":[{"id":"2308.05345","title":"RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model","created":"2023-08-10","cited_by_count":148,"area":null},{"id":"2305.13243","title":"Chip-Chat: Challenges and Opportunities in Conversational Hardware Design","created":"2023-05-22","cited_by_count":140,"area":null},{"id":"2111.14616","title":"DeepGate: Learning Neural Representations of Logic Gates","created":"2021-11-26","cited_by_count":37,"area":null},{"id":"2110.11292","title":"OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis","created":"2021-10-21","cited_by_count":30,"area":null},{"id":"2502.18297","title":"DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis","created":"2025-02-25","cited_by_count":21,"area":null},{"id":"2405.05349","title":"Offline Model-Based Optimization via Policy-Guided Gradient Search","created":"2024-05-08","cited_by_count":19,"area":null},{"id":"2111.06178","title":"BOiLS: Bayesian Optimisation for Logic Synthesis","created":"2021-11-11","cited_by_count":18,"area":null},{"id":"2406.04379","title":"VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation","created":"2024-06-06","cited_by_count":15,"area":null},{"id":"2212.11408","title":"Adaptive and Dynamic Multi-Resolution Hashing for Pairwise Summations","created":"2022-12-21","cited_by_count":14,"area":null},{"id":"2407.15026","title":"Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms","created":"2024-07-03","cited_by_count":14,"area":null},{"id":"2203.15913","title":"Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Design","created":"2022-03-29","cited_by_count":13,"area":null},{"id":"2208.01040","title":"CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)","created":"2022-08-01","cited_by_count":11,"area":null},{"id":"2406.09606","title":"Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis","created":"2024-06-13","cited_by_count":10,"area":null},{"id":"2509.04905","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","created":"2025-09-05","cited_by_count":9,"area":null},{"id":"2507.13369","title":"VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation","created":"2025-07-09","cited_by_count":8,"area":null},{"id":"2302.13608","title":"DeepSeq: Deep Sequential Circuit Learning","created":"2023-02-27","cited_by_count":7,"area":null},{"id":"2309.03208","title":"A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design","created":"2023-08-22","cited_by_count":6,"area":null},{"id":"2202.10015","title":"AI/ML Algorithms and Applications in VLSI Design and Technology","created":"2022-02-21","cited_by_count":5,"area":null},{"id":"2403.13838","title":"Circuit Transformer: A Transformer That Preserves Logical Equivalence","created":"2024-03-14","cited_by_count":5,"area":null},{"id":"2505.17866","title":"DesignX: Human-Competitive Algorithm Designer for Black-Box Optimization","created":"2025-05-23","cited_by_count":5,"area":null},{"id":"2507.02226","title":"DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs","created":"2025-07-03","cited_by_count":5,"area":null},{"id":"2202.13564","title":"Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview","created":"2022-02-28","cited_by_count":4,"area":null},{"id":"2305.14874","title":"From Words to Wires: Generating Functioning Electronic Devices from Natural Language Descriptions","created":"2023-05-24","cited_by_count":4,"area":null},{"id":"2308.11652","title":"Accelerating Exact Combinatorial Optimization via RL-based Initialization -- A Case Study in Scheduling","created":"2023-08-19","cited_by_count":4,"area":null},{"id":"2406.04699","title":"Logic Synthesis with Generative Deep Neural Networks","created":"2024-06-07","cited_by_count":4,"area":null},{"id":"2108.03978","title":"VeRLPy: Python Library for Verification of Digital Designs with Reinforcement Learning","created":"2021-08-09","cited_by_count":3,"area":null},{"id":"2211.16495","title":"Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs","created":"2022-11-29","cited_by_count":3,"area":null},{"id":"2411.00843","title":"The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation","created":"2024-10-30","cited_by_count":3,"area":null},{"id":"2411.09422","title":"OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis","created":"2024-11-14","cited_by_count":3,"area":null},{"id":"2601.19439","title":"OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation","created":"2026-01-27","cited_by_count":3,"area":null},{"id":"2306.12456","title":"Pushing the Limits of Machine Design: Automated CPU Design with AI","created":"2023-06-21","cited_by_count":2,"area":null},{"id":"2312.01674","title":"EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research","created":"2023-12-04","cited_by_count":2,"area":null},{"id":"2403.10686","title":"AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs","created":"2024-03-15","cited_by_count":2,"area":null},{"id":"2408.09858","title":"ShortCircuit: AlphaZero-Driven Circuit Design","created":"2024-08-19","cited_by_count":2,"area":null},{"id":"2409.06077","title":"MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization","created":"2024-09-09","cited_by_count":2,"area":null},{"id":"2410.00995","title":"CktGen: Automated Analog Circuit Design with Generative Artificial Intelligence","created":"2024-10-01","cited_by_count":2,"area":null},{"id":"2203.16009","title":"Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data","created":"2022-03-30","cited_by_count":1,"area":null},{"id":"2204.09579","title":"A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation","created":"2022-04-19","cited_by_count":1,"area":null},{"id":"2205.05664","title":"Process, Bias and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning","created":"2022-05-11","cited_by_count":1,"area":null},{"id":"2207.11312","title":"HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector Generation","created":"2022-07-22","cited_by_count":1,"area":null},{"id":"2405.01419","title":"Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT","created":"2024-05-02","cited_by_count":1,"area":null},{"id":"2409.10653","title":"Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers","created":"2024-09-16","cited_by_count":1,"area":null},{"id":"2503.11687","title":"Review of Machine Learning for Micro-Electronic Design Verification","created":"2025-03-05","cited_by_count":1,"area":null},{"id":"2505.09610","title":"Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors","created":"2025-05-14","cited_by_count":1,"area":null},{"id":"2506.06787","title":"FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks","created":"2025-06-07","cited_by_count":1,"area":null},{"id":"2506.10577","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","created":"2025-06-12","cited_by_count":1,"area":null},{"id":"2510.23643","title":"SAND: A Self-supervised and Adaptive NAS-Driven Framework for Hardware Trojan Detection","created":"2025-10-24","cited_by_count":1,"area":null},{"id":"2511.08315","title":"BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning","created":"2025-11-11","cited_by_count":1,"area":null},{"id":"2602.19330","title":"CTS-Bench: Benchmarking Graph Coarsening Trade-offs for GNNs in Clock Tree Synthesis","created":"2026-02-22","cited_by_count":1,"area":null},{"id":"2608.27184","title":"LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration","created":"2026-08-27","cited_by_count":1,"area":null},{"id":"2108.00257","title":"BoA-PTA, A Bayesian Optimization Accelerated Error-Free SPICE Solver","created":"2021-07-31","cited_by_count":0,"area":null},{"id":"2203.10597","title":"The Dark Side: Security Concerns in Machine Learning for EDA","created":"2022-03-20","cited_by_count":0,"area":null},{"id":"2206.03032","title":"Intelligent Circuit Design and Implementation with Machine Learning","created":"2022-06-07","cited_by_count":0,"area":null},{"id":"2305.10838","title":"ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation","created":"2023-05-18","cited_by_count":0,"area":null},{"id":"2308.03944","title":"GraPhSyM: Graph Physical Synthesis Model","created":"2023-08-07","cited_by_count":0,"area":null},{"id":"2308.11624","title":"Revolutionizing TCAD Simulations with Universal Device Encoding and Graph Attention Networks","created":"2023-08-01","cited_by_count":0,"area":null},{"id":"2311.17815","title":"A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures","created":"2023-11-29","cited_by_count":0,"area":null},{"id":"2312.01921","title":"A Machine Learning Approach Towards SKILL Code Autocompletion","created":"2023-12-04","cited_by_count":0,"area":null},{"id":"2412.21035","title":"Machine Learning Optimal Ordering in Global Routing Problems in Semiconductors","created":"2024-12-30","cited_by_count":0,"area":null},{"id":"2505.02105","title":"Deep Representation Learning for Electronic Design Automation","created":"2025-05-04","cited_by_count":0,"area":null},{"id":"2506.07126","title":"MAGNet: A Multi-Scale Attention-Guided Graph Fusion Network for DRC Violation Detection","created":"2025-06-08","cited_by_count":0,"area":null},{"id":"2508.11991","title":"Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Network","created":"2025-08-16","cited_by_count":0,"area":null},{"id":"2511.23340","title":"ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction","created":"2025-11-28","cited_by_count":0,"area":null},{"id":"2603.04450","title":"MPBMC: Multi-Property Bounded Model Checking with GNN-guided Clustering","created":"2026-02-26","cited_by_count":0,"area":null},{"id":"2604.10841","title":"Harnessing Photonics for Machine Intelligence","created":"2026-04-12","cited_by_count":0,"area":null},{"id":"2604.18445","title":"AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning","created":"2026-04-20","cited_by_count":0,"area":null},{"id":"2605.08291","title":"Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation","created":"2026-05-08","cited_by_count":0,"area":null},{"id":"2609.03594","title":"LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks","created":"2026-09-03","cited_by_count":0,"area":null},{"id":"2610.16625","title":"LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation","created":"2026-10-12","cited_by_count":0,"area":null}],"next_cursor":null}