{"total":41,"rows":[{"id":"2108.09293","title":"Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributions","created":"2021-08-20","cited_by_count":431,"area":null},{"id":"2308.00708","title":"VeriGen: A Large Language Model for Verilog Code Generation","created":"2023-07-28","cited_by_count":200,"area":null},{"id":"2311.00176","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","created":"2023-10-31","cited_by_count":174,"area":null},{"id":"2305.13243","title":"Chip-Chat: Challenges and Opportunities in Conversational Hardware Design","created":"2023-05-22","cited_by_count":140,"area":null},{"id":"2212.11140","title":"Benchmarking Large Language Models for Automated Verilog RTL Code Generation","created":"2022-12-13","cited_by_count":115,"area":null},{"id":"2410.03981","title":"A Survey on LLM-based Code Generation for Low-Resource and Domain-Specific Programming Languages","created":"2024-10-04","cited_by_count":66,"area":null},{"id":"2407.16237","title":"OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection","created":"2024-07-23","cited_by_count":56,"area":null},{"id":"2402.03289","title":"Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS","created":"2024-02-05","cited_by_count":43,"area":null},{"id":"2403.11202","title":"Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework","created":"2024-03-17","cited_by_count":36,"area":null},{"id":"2306.14027","title":"(Security) Assertions by Large Language Models","created":"2023-06-24","cited_by_count":32,"area":null},{"id":"2502.15832","title":"DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model","created":"2025-02-20","cited_by_count":23,"area":null},{"id":"2405.07061","title":"LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust","created":"2024-05-11","cited_by_count":20,"area":null},{"id":"2404.08806","title":"CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation","created":"2024-04-12","cited_by_count":19,"area":null},{"id":"2411.11856","title":"Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback","created":"2024-11-01","cited_by_count":19,"area":null},{"id":"2304.13840","title":"A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation","created":"2023-04-26","cited_by_count":10,"area":null},{"id":"2410.23299","title":"FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware","created":"2024-10-15","cited_by_count":10,"area":null},{"id":"2405.02326","title":"Evaluating LLMs for Hardware Design and Test","created":"2024-04-23","cited_by_count":8,"area":null},{"id":"2508.05266","title":"Understanding and Mitigating Errors of LLM-Generated RTL Code","created":"2025-08-07","cited_by_count":8,"area":null},{"id":"2512.00020","title":"Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead","created":"2025-10-29","cited_by_count":8,"area":null},{"id":"2506.00005","title":"Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form","created":"2025-05-07","cited_by_count":7,"area":null},{"id":"2405.16072","title":"SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generation","created":"2024-05-25","cited_by_count":6,"area":null},{"id":"2505.19734","title":"ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection","created":"2025-05-26","cited_by_count":6,"area":null},{"id":"2507.12308","title":"Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization","created":"2025-07-16","cited_by_count":6,"area":null},{"id":"2401.08683","title":"Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Models","created":"2024-01-12","cited_by_count":5,"area":null},{"id":"2411.15442","title":"Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting","created":"2024-11-23","cited_by_count":4,"area":null},{"id":"2507.06512","title":"Towards LLM-based Root Cause Analysis of Hardware Design Failures","created":"2025-07-09","cited_by_count":4,"area":null},{"id":"2510.19296","title":"QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation","created":"2025-10-22","cited_by_count":4,"area":null},{"id":"2404.07235","title":"LLM-aided explanations of EDA synthesis errors","created":"2024-04-07","cited_by_count":3,"area":null},{"id":"2508.20030","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","created":"2025-08-27","cited_by_count":3,"area":null},{"id":"2311.03489","title":"Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design","created":"2023-11-06","cited_by_count":2,"area":null},{"id":"2503.05951","title":"TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator","created":"2025-03-07","cited_by_count":2,"area":null},{"id":"2310.10560","title":"Towards the Imagenets of ML4EDA","created":"2023-10-16","cited_by_count":1,"area":null},{"id":"2407.12749","title":"ChipXplore: Natural Language Exploration of Hardware Designs and Libraries","created":"2024-07-17","cited_by_count":1,"area":null},{"id":"2506.00001","title":"Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering Techniques","created":"2025-03-26","cited_by_count":1,"area":null},{"id":"2511.20099","title":"QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design","created":"2025-11-25","cited_by_count":1,"area":null},{"id":"2312.01921","title":"A Machine Learning Approach Towards SKILL Code Autocompletion","created":"2023-12-04","cited_by_count":0,"area":null},{"id":"2506.05007","title":"QiMeng: Fully Automated Hardware and Software Design for Processor Chip","created":"2025-06-05","cited_by_count":0,"area":null},{"id":"2602.19297","title":"Automated Generation of Microfluidic Netlists using Large Language Models","created":"2026-02-22","cited_by_count":0,"area":null},{"id":"2605.07782","title":"CktFormalizer: Autoformalization of Natural Language into Circuit Representations","created":"2026-05-08","cited_by_count":0,"area":null},{"id":"2606.10285","title":"OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design","created":"2026-06-09","cited_by_count":0,"area":null},{"id":"2610.05380","title":"VHDL-REPOBENCH: A Repository-Level Benchmark for Evaluating Large Language Models on VHDL Design Generation","created":"2026-10-04","cited_by_count":0,"area":null}],"next_cursor":null}