{"total":41,"rows":[{"id":"2102.02770","title":"A Living Review of Machine Learning for Particle Physics","created":"2021-02-02","cited_by_count":78,"area":null},{"id":"2103.05579","title":"hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices","created":"2021-03-09","cited_by_count":62,"area":null},{"id":"2101.05108","title":"Fast convolutional neural networks on FPGAs with hls4ml","created":"2021-01-13","cited_by_count":42,"area":null},{"id":"2110.13041","title":"Applications and Techniques for Fast Machine Learning in Science","created":"2021-10-25","cited_by_count":32,"area":null},{"id":"2102.11289","title":"Ps and Qs: Quantization-aware pruning for efficient low latency neural network inference","created":"2021-02-22","cited_by_count":31,"area":null},{"id":"2309.02334","title":"PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference","created":"2023-09-05","cited_by_count":30,"area":null},{"id":"2403.00849","title":"NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions","created":"2024-02-29","cited_by_count":21,"area":null},{"id":"2103.16701","title":"Charged particle tracking via edge-classifying interaction networks","created":"2021-03-30","cited_by_count":19,"area":null},{"id":"2112.02048","title":"Graph Neural Networks for Charged Particle Tracking on FPGAs","created":"2021-12-03","cited_by_count":17,"area":null},{"id":"2207.00559","title":"Ultra-low latency recurrent neural network inference on FPGAs for physics applications with hls4ml","created":"2022-07-01","cited_by_count":14,"area":null},{"id":"2504.00592","title":"NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference","created":"2025-04-01","cited_by_count":14,"area":null},{"id":"2512.12850","title":"KANEL\\'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation","created":"2025-12-14","cited_by_count":13,"area":null},{"id":"2203.12852","title":"Graph Neural Networks in Particle Physics: Implementations, Innovations, and Challenges","created":"2022-03-23","cited_by_count":12,"area":null},{"id":"2406.04910","title":"PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs","created":"2024-06-07","cited_by_count":12,"area":null},{"id":"2205.07690","title":"Real-time semantic segmentation on FPGAs for autonomous vehicles with hls4ml","created":"2022-05-16","cited_by_count":11,"area":null},{"id":"2209.07559","title":"Snowmass 2021 Computational Frontier CompF03 Topical Group Report: Machine Learning","created":"2022-09-15","cited_by_count":10,"area":null},{"id":"2104.03408","title":"Nanosecond machine learning event classification with boosted decision trees in FPGA for high energy physics","created":"2021-04-07","cited_by_count":9,"area":null},{"id":"2206.11791","title":"Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark","created":"2022-06-23","cited_by_count":9,"area":null},{"id":"2512.01463","title":"hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware","created":"2025-12-01","cited_by_count":9,"area":null},{"id":"2501.08043","title":"PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruning","created":"2025-01-14","cited_by_count":8,"area":null},{"id":"2308.05170","title":"FPGA Resource-aware Structured Pruning for Real-Time Neural Networks","created":"2023-08-09","cited_by_count":7,"area":null},{"id":"2510.24784","title":"Sub-microsecond Transformers for Jet Tagging on FPGAs","created":"2025-10-26","cited_by_count":6,"area":null},{"id":"2307.05152","title":"Fast Neural Network Inference on FPGAs for Triggering on Long-Lived Particles at Colliders","created":"2023-07-11","cited_by_count":5,"area":null},{"id":"2512.15946","title":"AIE4ML: An End-to-End Framework for Compiling Neural Networks for the Next Generation of AMD AI Engines","created":"2025-12-17","cited_by_count":5,"area":null},{"id":"2304.08400","title":"ATHEENA: A Toolflow for Hardware Early-Exit Network Automation","created":"2023-04-17","cited_by_count":3,"area":null},{"id":"2203.16255","title":"Physics Community Needs, Tools, and Resources for Machine Learning","created":"2022-03-30","cited_by_count":2,"area":null},{"id":"2303.01505","title":"Ternary Quantization: A Survey","created":"2023-03-02","cited_by_count":2,"area":null},{"id":"2304.06745","title":"End-to-end codesign of Hessian-aware quantized neural networks for FPGAs and ASICs","created":"2023-04-13","cited_by_count":2,"area":null},{"id":"2503.12829","title":"SparseLUT: Sparse Connectivity Optimization for Lookup Table-based Deep Neural Networks","created":"2025-03-17","cited_by_count":2,"area":null},{"id":"2402.02593","title":"Leveraging Continuously Differentiable Activation Functions for Learning in Quantized Noisy Environments","created":"2024-02-04","cited_by_count":1,"area":null},{"id":"2502.07823","title":"Runtime Tunable Tsetlin Machines for Edge Inference on eFPGAs","created":"2025-02-10","cited_by_count":1,"area":null},{"id":"2502.08692","title":"Efficient Split Learning LSTM Models for FPGA-based Edge IoT Devices","created":"2025-02-12","cited_by_count":1,"area":null},{"id":"2504.03387","title":"BitHEP -- The Limits of Low-Precision ML in HEP","created":"2025-04-04","cited_by_count":1,"area":null},{"id":"2602.23455","title":"BiKA: Kolmogorov-Arnold-Network-inspired Ultra Lightweight Neural Network Hardware Accelerator","created":"2026-02-26","cited_by_count":1,"area":null},{"id":"2604.22293","title":"HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference","created":"2026-04-24","cited_by_count":1,"area":null},{"id":"2606.10008","title":"Spiking Neural Network inference on FPGAs with hls4ml","created":"2026-06-08","cited_by_count":1,"area":null},{"id":"2306.06743","title":"Trees versus Neural Networks for enhancing tau lepton real-time selection in proton-proton collisions","created":"2023-06-11","cited_by_count":0,"area":null},{"id":"2601.09773","title":"Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization","created":"2026-01-14","cited_by_count":0,"area":null},{"id":"2601.19920","title":"PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator","created":"2026-01-08","cited_by_count":0,"area":null},{"id":"2608.00720","title":"CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs","created":"2026-08-01","cited_by_count":0,"area":null},{"id":"2609.09254","title":"DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity","created":"2026-09-08","cited_by_count":0,"area":null}],"next_cursor":null}