{"total":17,"rows":[{"id":"2102.03357","title":"Machine Learning for Electronic Design Automation: A Survey","created":"2021-01-10","cited_by_count":72,"area":null},{"id":"2102.07952","title":"A Survey of Machine Learning for Computer Architecture and Systems","created":"2021-02-16","cited_by_count":53,"area":null},{"id":"2102.08138","title":"IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning","created":"2021-02-16","cited_by_count":26,"area":null},{"id":"2201.06848","title":"High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing","created":"2022-01-18","cited_by_count":26,"area":null},{"id":"2405.00820","title":"HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond","created":"2024-05-01","cited_by_count":8,"area":null},{"id":"2401.08696","title":"Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs","created":"2024-01-14","cited_by_count":5,"area":null},{"id":"2408.05314","title":"rule4ml: An Open-Source Tool for Resource Utilization and Latency Estimation for ML Models on FPGA","created":"2024-08-09","cited_by_count":3,"area":null},{"id":"2306.12456","title":"Pushing the Limits of Machine Design: Automated CPU Design with AI","created":"2023-06-21","cited_by_count":2,"area":null},{"id":"2403.10686","title":"AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs","created":"2024-03-15","cited_by_count":2,"area":null},{"id":"2204.09579","title":"A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation","created":"2022-04-19","cited_by_count":1,"area":null},{"id":"2208.10606","title":"LEAPER: Fast and Accurate FPGA-based System Performance Prediction via Transfer Learning","created":"2022-08-22","cited_by_count":1,"area":null},{"id":"2410.06460","title":"A Benchmark on Directed Graph Representation Learning in Hardware Designs","created":"2024-10-09","cited_by_count":1,"area":null},{"id":"2505.13461","title":"FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Review","created":"2025-05-04","cited_by_count":1,"area":null},{"id":"2601.14541","title":"Report for NSF Workshop on AI for Electronic Design Automation","created":"2026-01-20","cited_by_count":1,"area":null},{"id":"2203.10597","title":"The Dark Side: Security Concerns in Machine Learning for EDA","created":"2022-03-20","cited_by_count":0,"area":null},{"id":"2308.03944","title":"GraPhSyM: Graph Physical Synthesis Model","created":"2023-08-07","cited_by_count":0,"area":null},{"id":"2506.05007","title":"QiMeng: Fully Automated Hardware and Software Design for Processor Chip","created":"2025-06-05","cited_by_count":0,"area":null}],"next_cursor":null}