{"total":27,"rows":[{"id":"2307.07982","title":"A Survey of Techniques for Optimizing Transformer Inference","created":"2023-07-16","cited_by_count":35,"area":null},{"id":"2107.07983","title":"S2TA: Exploiting Structured Sparsity for Energy-Efficient Mobile CNN Acceleration","created":"2021-07-16","cited_by_count":19,"area":null},{"id":"2411.11745","title":"BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration","created":"2024-11-18","cited_by_count":18,"area":null},{"id":"2209.00606","title":"Sparse Attention Acceleration with Synergistic In-Memory Pruning and On-Chip Recomputation","created":"2022-09-01","cited_by_count":12,"area":null},{"id":"2106.15315","title":"Boggart: Towards General-Purpose Acceleration of Retrospective Video Analytics","created":"2021-06-21","cited_by_count":10,"area":null},{"id":"2204.03227","title":"Accelerating Attention through Gradient-Based Learned Runtime Pruning","created":"2022-04-07","cited_by_count":8,"area":null},{"id":"2304.10618","title":"ULEEN: A Novel Architecture for Ultra Low-Energy Edge Neural Networks","created":"2023-04-20","cited_by_count":8,"area":null},{"id":"2505.10909","title":"Phi: Leveraging Pattern-based Hierarchical Sparsity for High-Efficiency Spiking Neural Networks","created":"2025-05-16","cited_by_count":5,"area":null},{"id":"2101.11748","title":"Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators","created":"2021-01-27","cited_by_count":4,"area":null},{"id":"2103.05600","title":"unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation","created":"2021-03-09","cited_by_count":4,"area":null},{"id":"2409.05227","title":"BBS: Bi-directional Bit-level Sparsity for Deep Learning Acceleration","created":"2024-09-08","cited_by_count":3,"area":null},{"id":"2106.15021","title":"How to Reach Real-Time AI on Consumer Devices? Solutions for Programmable and Custom Architectures","created":"2021-06-21","cited_by_count":2,"area":null},{"id":"2306.09552","title":"Retrospective: EIE: Efficient Inference Engine on Sparse and Compressed Neural Network","created":"2023-06-15","cited_by_count":2,"area":null},{"id":"2506.23717","title":"Towards Efficient and Accurate Spiking Neural Networks via Adaptive Bit Allocation","created":"2025-06-30","cited_by_count":2,"area":null},{"id":"2103.01308","title":"SWIS -- Shared Weight bIt Sparsity for Efficient Neural Network Acceleration","created":"2021-03-01","cited_by_count":1,"area":null},{"id":"2211.05276","title":"PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator","created":"2022-11-10","cited_by_count":1,"area":null},{"id":"2307.13412","title":"Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation","created":"2023-07-25","cited_by_count":1,"area":null},{"id":"2412.13724","title":"USEFUSE: Uniform Stride for Enhanced Performance in Fused Layer Architecture of Deep Neural Networks","created":"2024-12-18","cited_by_count":1,"area":null},{"id":"2607.05445","title":"BitFair: A 12-nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision","created":"2026-07-04","cited_by_count":1,"area":null},{"id":"2101.01163","title":"SmartDeal: Re-Modeling Deep Network Weights for Efficient Inference and Training","created":"2021-01-04","cited_by_count":0,"area":null},{"id":"2101.08884","title":"Direct Spatial Implementation of Sparse Matrix Multipliers for Reservoir Computing","created":"2021-01-21","cited_by_count":0,"area":null},{"id":"2104.05541","title":"Optimizing the Whole-life Cost in End-to-end CNN Acceleration","created":"2021-04-12","cited_by_count":0,"area":null},{"id":"2411.15209","title":"QABBA: Symbolic Time-Series Compression via Integer-Quantized Aggregation","created":"2024-11-20","cited_by_count":0,"area":null},{"id":"2503.06342","title":"Exploring the Performance Improvement of Tensor Processing Engines through Transformation in the Bit-weight Dimension of MACs","created":"2025-03-08","cited_by_count":0,"area":null},{"id":"2507.09780","title":"BitParticle: Partializing Sparse Dual-Factors to Build Quasi-Synchronizing MAC Arrays for Energy-efficient DNNs","created":"2025-07-13","cited_by_count":0,"area":null},{"id":"2603.10100","title":"Hardware Efficient Approximate Convolution with Tunable Error Tolerance for CNNs","created":"2026-03-10","cited_by_count":0,"area":null},{"id":"2607.19431","title":"BRIM: Workload-Balanced Dual-Sided Bit-Serial Sparse Inference Accelerator","created":"2026-07-20","cited_by_count":0,"area":null}],"next_cursor":null}